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  • PowerPCB教程簡介 歡迎使用 PowerPCB 教程。本教程描述了PADS-PowerPCB 的絕大部分功能 和特點

    PowerPCB教程簡介 歡迎使用 PowerPCB 教程。本教程描述了PADS-PowerPCB 的絕大部分功能 和特點,以及使用的各個過程,這些功能包括: · 基本操作 · 建立元件(Component) · 建立板子邊框線(Board outline) · 輸入網表(Netlist) · 設置設計規則(Design Rule) ·元件(Part)的布局(Placement) · 手工和交互的布線 · SPECCTRA全自動布線器(Route Engine) ·覆銅(Copper Pour) · 建立分隔/混合平面層(Split/mixed Plane) · Microsoft 的目標連接與嵌入(OLE)(Object Linking Embedding) · 可選擇的裝配選件(Assembly options) · 設計規則檢查(Design Rule Check) · 反向標注(Back Annotation) · 繪圖輸出(Plot Output) 使用本教程后,你可以學到印制電路板設計和制造的許多基本知識。 你不必一次完成整個教程,如果在任何時候退出后,下次直接找到你要進入 的部分,繼續學習本教程。 當你完成了本教程的學習后,可以參考在線幫助(On-line Help)以便得到更多 的信息。如果你需要附加的信息內容,你可以與PADS 在各地辦事處或代理商取 得聯系,以便得到更多的幫助。 歡迎使用PowerPCB進行PCB設計!

    標簽: PowerPCB PADS-PowerPCB 教程

    上傳時間: 2013-12-12

    上傳用戶:caozhizhi

  • 葉輪機械多級葉輪網格生成程序介紹 侯 樂 毅 非定常流課題組 本文開發的葉輪機械多級葉輪網格生成程序

    葉輪機械多級葉輪網格生成程序介紹 侯 樂 毅 非定常流課題組 本文開發的葉輪機械多級葉輪網格生成程序,采用的網格類型為H型,并在葉片前面/后面延伸區域設置平直網格數ID1和IDN。主程序MESH_BLADE_STAGES,分成三個部分,原始葉型及控制參數從輸入程序INPUT輸入,求解程序為GRID(ZERO),輸出程序為Output

    標簽: 輪機 多級 網格 程序

    上傳時間: 2013-12-03

    上傳用戶:bjgaofei

  • In this project we analyze and design the minimum mean-square error (MMSE) multiuser receiver for un

    In this project we analyze and design the minimum mean-square error (MMSE) multiuser receiver for uniformly quantized synchronous code division multiple access (CDMA) signals in additive white Gaussian noise (AWGN) channels.This project is mainly based on the representation of uniform quantizer by gain plus additive noise model. Based on this model, we derive the weight vector and the Output signal-to-interference ratio (SIR) of the MMSE receiver. The effects of quantization on the MMSE receiver performance is characterized in a single parameter named 鈥漞quivalent noise variance鈥? The optimal quantizer stepsize which maximizes the MMSE receiver Output SNR is also determined.

    標簽: mean-square multiuser receiver project

    上傳時間: 2014-11-21

    上傳用戶:ywqaxiwang

  • This Telecommunication Standard [TS] describes the detailed mapping from input blocks of 160 speech

    This Telecommunication Standard [TS] describes the detailed mapping from input blocks of 160 speech samples in 13-bit uniform PCM format to encoded blocks of 95, 103, 118, 134, 148, 159, 204, and 244 bits and from encoded blocks of 95, 103, 118, 134, 148, 159, 204, and 244 bits to Output blocks of 160 reconstructed speech samples

    標簽: Telecommunication describes Standard detailed

    上傳時間: 2013-12-12

    上傳用戶:cuibaigao

  • 3rd Generation Partnership Project Technical Specification Group Radio Access Network Spatial ch

    3rd Generation Partnership Project Technical Specification Group Radio Access Network Spatial channel model for Multiple Input Multiple Output [MIMO] simulations

    標簽: Specification Partnership Generation Technical

    上傳時間: 2014-01-11

    上傳用戶:nanfeicui

  • This is a source of 13.560MHz RFID card reader for TRH031M as ATMEGA8-16AU MPU. The title is 3Alogi

    This is a source of 13.560MHz RFID card reader for TRH031M as ATMEGA8-16AU MPU. The title is 3Alogics TRH031M 13.56MHz RFID Reader V1.0. project : RFID Reader V2.0 Target : MEGA8-16AU Crystal: 16.000 Mhz Input : TRH031M RFID 13.56MHz Output : RS232C 115200,N,8,1 Compiler : ICC-AVR V6.26C // Pin configuration for ATMEGA8-16AU TQFP32 // #30 RXD <--- RXD (SP3232) // #31 TXD ---> TXD (SP3232) // #32 PD2/INT0 <--- INTR (TRH031M) // # 1 PD3/INT1 ---> RST (TRH031M) // # 2 PD4 ---> D4 (TRH031M) // # 9 PD5 ---> D5 (TRH031M) // #10 PD6 ---> D6 (TRH031M) // #11 PD7 ---> D7 (TRH031M) // #12 PB0 ---> D0 (TRH031M) // #13 PB1 ---> D1 (TRH031M) // #14 PB2 ---> D2 (TRH031M) // #15 PB3 ---> D3 (TRH031M) // #16 PB4 ---> CSB (TRH031M) // #17 PB5 ---> LED // #23 PC0 ---> A0 (TRH031M) // #24 PC1 ---> A1 (TRH031M) // #25 PC2 ---> A2 (TRH031M) // #26 PC3 ---> ALE (TRH031M) // #27 PC4 ---> /RD (TRH031M) // #28 PC5 ---> /WR (TRH031M)

    標簽: 13.560 ATMEGA 3Alogi source

    上傳時間: 2017-03-31

    上傳用戶:s363994250

  • DESCRIPTION The DCP0105 family is a series of high efficiency, 5V input isolated DC/DC converters.

    DESCRIPTION The DCP0105 family is a series of high efficiency, 5V input isolated DC/DC converters. In addition to 1W nominal galvanically isolated Output power capability, the range of DC/DCs are also fully synchronizable. The devices feature thermal shutdown, and overload protection is implemented via watchdog circuitry. Advanced power-on reset techniques give superior reset performance and the devices will start into any capacitive load up to full power Output. The DCP0105 family is implemented in standard- molded IC packaging, giving outlines suitable for high volume assembly.

    標簽: DESCRIPTION efficiency converters isolated

    上傳時間: 2013-11-28

    上傳用戶:CHENKAI

  • 使用FPGA/CPLD設置語音AD、DA轉換芯片AIC23

    使用FPGA/CPLD設置語音AD、DA轉換芯片AIC23,FPGA/CPLD系統時鐘為24.576MHz 1、AIC系統時鐘為12.288MHz,SPI時鐘為6.144MHz 2、AIC處于主控模式 3、input bit length 16bit Output bit length 16bit MSB first 4、幀同步在96KHz

    標簽: FPGA CPLD AIC 23

    上傳時間: 2013-12-20

    上傳用戶:二驅蚊器

  • c pgm to find redundant paths in a graph.Many fault-tolerant network algorithms rely on an underlyin

    c pgm to find redundant paths in a graph.Many fault-tolerant network algorithms rely on an underlying assumption that there are possibly distinct network paths between a source-destination pair. Given a directed graph as input, write a program that uses depth-first search to determine all such paths. Note that, these paths are not vertex-disjoint i.e., the vertices may repeat but they are all edge-disjoint i.e., no two paths have the same edges. The input is the adjacency matrix of a directed acyclic graph and a pair(s) of source and destination vertices and the Output should be the number of such disjoint paths and the paths themselves on separate lines. In case of multiple paths the Output should be in order of paths with minimum vertices first. In case of tie the vertex number should be taken in consideration for ordering.

    標簽: fault-tolerant algorithms redundant underlyin

    上傳時間: 2013-12-18

    上傳用戶:jkhjkh1982

  • Shortest Paths with Multiplicative Cost. In a given undirected graph, the path cost is measured as a

    Shortest Paths with Multiplicative Cost. In a given undirected graph, the path cost is measured as a product of all the edges in the path. The weights are rational numbers (e.g., 0.25, 0.75, 3.75 etc) or integers (2, 3). There are no negative edges. Given such a graph as input, you are to Output the shortest path between any two given vertices. Input is the adjacency matrix and the two vertices. You must Output the path.

    標簽: Multiplicative undirected Shortest measured

    上傳時間: 2017-04-08

    上傳用戶:邶刖

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