基于TMS320F2812 光伏并網(wǎng)發(fā)電模擬裝置PROTEL設(shè)計原理圖+PCB+軟件源碼+WORD論文文檔,硬件采用2層板設(shè)計，PROTEL99SE 設(shè)計的工程文件，包括完整的原理圖和PCB文件，可以做為你的學(xué)習(xí)設(shè)計參考。 摘要：本文實(shí)現(xiàn)了一個基于TMS320F2812 DSP芯片的光伏并網(wǎng)發(fā)電模擬裝置，采用直流穩(wěn)壓源和滑動變阻器來模擬光伏電池。通過TMS320F2812 DSP芯片ADC模塊實(shí)時采樣模擬電網(wǎng)電壓的正弦參考信號、光伏電池輸出電壓、負(fù)載電壓電流反饋信號等。經(jīng)過數(shù)據(jù)處理后，用PWM模塊產(chǎn)生實(shí)時的SPWM 波，控制MOSFET逆變?nèi)珮蜉敵稣也ā１疚挠肞I控制算法實(shí)現(xiàn)了輸出信號對給定模擬電網(wǎng)電壓的正弦參考信號的頻率和相位跟蹤，用恒定電壓法實(shí)現(xiàn)了光伏電池最大功率點(diǎn)跟蹤（MPPT），從而達(dá)到模擬并網(wǎng)的效果。另外本裝置還實(shí)現(xiàn)了光伏電池輸出欠壓、負(fù)載過流保護(hù)功能以及光伏電池輸出欠壓、過流保護(hù)自恢復(fù)功能、聲光報警功能、孤島效應(yīng)的檢測、保護(hù)與自恢復(fù)功能。系統(tǒng)測試結(jié)果表明本設(shè)計完全滿定設(shè)計要求。關(guān)鍵詞：光伏并網(wǎng)，MPPT，DSP Photovoltaic Grid-connected generation simulator Zhangyuxin，Tantiancheng，Xiewuyang(College of Electrical Engineering, Chongqing University)Abstract: This paper presents a photovoltaic grid-connected generation simulator which is based on TMS320F2812 DSP, with a DC voltage source and a variable resistor to simulate the characteristic of photovoltaic cells. We use the internal AD converter to real-time sampling the referenced grid voltage signal, outputting voltage of photovoltaic, feedback outputting voltage and current signal. The PWM module generates SVPWM according to the calculation of the real-time sampling data, to control the full MOSFET inverter bridge output sine wave. We realized that the output voltage of the simulator can track the frequency and phase of the referenced grid voltage with PI regulation, and the maximum photovoltaic power tracking with constant voltage regulation, thereby achieved the purpose of grid-connected simulation. Additionally, this device has the over-voltage and over-current protection, audible and visual alarm, islanding detecting and protection, and it can recover automatically. The testing shows that our design is feasible.Keywords: Photovoltaic Grid-connected，MPPT，DSP 目錄引言 11. 方案論證 11.1. 總體介紹 11.2. 光伏電池模擬裝置 11.3. DC-AC逆變橋 11.4. MOSFET驅(qū)動電路方案 21.5. 逆變電路的變頻控制方案 22. 理論分析與計算 22.1. SPWM產(chǎn)生 22.1.1. 規(guī)則采樣法 22.1.2. SPWM 脈沖的計算公式 32.1.3. SPWM 脈沖計算公式中的參數(shù)計算 32.1.4. TMS320F2812 DSP控制器的事件管理單元 42.1.5. 軟件設(shè)計方法 62.2. MPPT的控制方法與參數(shù)計算 72.3. 同頻、同相的控制方法和參數(shù)計算 8
標(biāo)簽： tms320f2812 光伏 并網(wǎng)發(fā)電 模擬 protel pcb
上傳時間： 2021-11-02
上傳用戶：
IIC接口E2PROM(AT24C64) 讀寫VERILOG 驅(qū)動源碼+仿真激勵文件:module i2c_dri #( parameter SLAVE_ADDR = 7'b1010000 , //EEPROM從機(jī)地址 parameter CLK_FREQ = 26'd50_000_000, //模塊輸入的時鐘頻率 parameter I2C_FREQ = 18'd250_000 //IIC_SCL的時鐘頻率 ) ( input clk , input rst_n , //i2c interface input i2c_exec , //I2C觸發(fā)執(zhí)行信號 input bit_ctrl , //字地址位控制(16b/8b) input i2c_rh_wl , //I2C讀寫控制信號 input [15:0] i2c_addr , //I2C器件內(nèi)地址 input [ 7:0] i2c_data_w , //I2C要寫的數(shù)據(jù) output reg [ 7:0] i2c_data_r , //I2C讀出的數(shù)據(jù) output reg i2c_done , //I2C一次操作完成 output reg i2c_ack , //I2C應(yīng)答標(biāo)志 0:應(yīng)答 1:未應(yīng)答 output reg scl , //I2C的SCL時鐘信號 inout sda , //I2C的SDA信號 //user interface output reg dri_clk //驅(qū)動I2C操作的驅(qū)動時鐘 );//localparam definelocalparam st_idle = 8'b0000_0001; //空閑狀態(tài)localparam st_sladdr = 8'b0000_0010; //發(fā)送器件地址(slave address)localparam st_addr16 = 8'b0000_0100; //發(fā)送16位字地址localparam st_addr8 = 8'b0000_1000; //發(fā)送8位字地址localparam st_data_wr = 8'b0001_0000; //寫數(shù)據(jù)(8 bit)localparam st_addr_rd = 8'b0010_0000; //發(fā)送器件地址讀localparam st_data_rd = 8'b0100_0000; //讀數(shù)據(jù)(8 bit)localparam st_stop = 8'b1000_0000; //結(jié)束I2C操作//reg definereg sda_dir ; //I2C數(shù)據(jù)(SDA)方向控制reg sda_out ; //SDA輸出信號reg st_done ; //狀態(tài)結(jié)束reg wr_flag ; //寫標(biāo)志reg [ 6:0] cnt ; //計數(shù)reg [ 7:0] cur_state ; //狀態(tài)機(jī)當(dāng)前狀態(tài)reg [ 7:0] next_state; //狀態(tài)機(jī)下一狀態(tài)reg [15:0] addr_t ; //地址reg [ 7:0] data_r ; //讀取的數(shù)據(jù)reg [ 7:0] data_wr_t ; //I2C需寫的數(shù)據(jù)的臨時寄存reg [ 9:0] clk_cnt ; //分頻時
標(biāo)簽： iic 接口 e2prom at24c64 verilog 驅(qū)動 仿真
上傳時間： 2021-11-05
上傳用戶：
ABSTRACTThe flyback power stage is a popular choice for single and multiple output dc-to-dc converters at powerlevels of 150 Watts or less. Without the output inductor required in buck derived topologies, such as theforward or push-pull converter, the component count and cost are reduced. This application note will reviewthe design procedure for the power stage and control electronics of a flyback converter. In these isolatedconverters, the error signal from the secondary still needs to cross the isolation boundary to achieveregulation. By using the UC3965 Precision Reference with Low Offset Error Amplifier on the secondaryside to drive an optocoupler and the UCC3809 Economy Primary Side Controller on the primary side, asimple and low cost 50 Watt isolated power supply is realized.
標(biāo)簽： 隔離
上傳時間： 2021-11-24
上傳用戶：kingwide
General Design Specification:1. AC Input Range 180-264Vac, Isolated ac-dc offline, 12LEDS,Output 700mA2. Intelligent wall dimmer detections(Leading-edge dimmer , Trailing-edgedimmer , No-dimmer)3. Multiple dimming control scheme4. Wide dimming range from 1% up to 100%5. No visible flicker6. Resonant control to achieve high efficiency7. High Power Factor, 0.9 without dimmer8. Temperature degrade control to adjust the LED9. Primary-only Sensing eliminates opto-isolator feedback and simplifies design
標(biāo)簽： iw3617
上傳時間： 2021-12-03
上傳用戶：canderile
FPGA讀取OV5640攝像頭數(shù)據(jù)并通過VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說明，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設(shè)計的字符VGA LCD顯示實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說明,通過字符轉(zhuǎn)換工具將字符轉(zhuǎn)換為 8 進(jìn)制 mif 文件存放到單端口的 ROM IP 核中，再從ROM 中把轉(zhuǎn)換后的數(shù)據(jù)讀取出來顯示到 VGA 上，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設(shè)計的sdram讀寫測試實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號,容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數(shù)據(jù)寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號都是時鐘信號。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標(biāo)簽： fpga sdram verilog quartus
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設(shè)計的vga顯示測試實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說明，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r = video_r[7:3]; //discard low bit dataassign vga_out_g = video_g[7:2]; //discard low bit dataassign vga_out_b = video_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule
標(biāo)簽： fpga vga顯示 verilog quartus
上傳時間： 2021-12-19
上傳用戶：kingwide
Texas instruments MIPI DSI to eDP converter. Input supports 2 channel, 4 lanes each, up to 1.5GBit/s. Total input bandwidth is 12Gbit/s. Output eDP 1.4 1,2 or 4 lanes up to 5.4Gbit/s. output up to 4096x2304 60fps.
上傳時間： 2021-12-22
上傳用戶：
高通(Qualcomm)藍(lán)牙芯片QCC5151_硬件設(shè)計詳細(xì)指導(dǎo)書（官方內(nèi)部培訓(xùn)手冊）共52頁其內(nèi)容是針對硬件設(shè)計、部分重要元器件選擇(ESD，F(xiàn)ilter）及走線注意事項(xiàng)的詳細(xì)說明。2 Power management 2.1 SMPS 2.1.1 Components specification 2.1.2 Input power supply selection 2.1.3 Minimize SMPS EMI emissions 2.1.4 Internal LDOs and digital core decoupling 2.1.5 Powering external components 2.2 Charger 2.2.1 Charger connections.2.2.2 General charger operation2.2.3 Temperature measurement during charging 2.3 SYS_CTRL 3 Bluetooth radio3.1 RF PSU component choice 3.2 RF band-pass filter3.3 Layout (天線 走線的注意事項(xiàng))4 Audio4.1 Audio bypass capacitors 4.2 Earphone speaker output4.3 Line/Mic input 4.4 Headphone output optimizition5 LED pads 5.1 LED driver 5.2 Digital/Button input 5.3 Analog input5.4 Disabled 6 Reset pin (Reset#)7 QSPIinterface 8 USB interfaces 8.1 USB device port8.1.1 USB connections8.1.2 Layout notes8.1.3 USB charger detection
標(biāo)簽： qualcomm 藍(lán)牙芯片 qcc5151
上傳時間： 2022-01-24
上傳用戶：XuVshu
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