The family of recent wireless standards included the optional employment of Multiple-Input Multiple-Output(MIMO)techniques.This was motivatedby the observationaccordingto the classic Shannon–Hartley law that the achievable channel capacity increases logarithmically with the transmit power. In contrast, the MIMO capacity increases linearly with the number of transmit antennas, provided that the number of receive antennas is equal to the number of transmit antennas. With the further proviso that the total transmit power is increased in proportion to the number of transmit antennas, a linear capacity increase is achieved upon increasing the transmit power, which justifies the spectacular success of MIMO systems.
標簽： Multi-Functional Systems MIMO
上傳時間： 2020-05-31
上傳用戶：shancjb
The purpose of this book is to introduce the concept of the Multiple Input Multiple Output (MIMO) radio channel, which is an intelligent communication method based upon using multiple antennas. The book opens by explaining MIMO in layman’s terms to help stu- dents and people in industry working in related areas become easily familiarised with the concept. Therefore the structure of the book will be carefully arranged to allow a user to progress steadily through the chapters and understand the fundamental and mathematical principles behind MIMO through the visual and explanatory way in which they will be written. It is the intention that several references will also be provided, leading to further reading in this highly researched technology.
上傳時間： 2020-05-31
上傳用戶：shancjb
The multiple-input multiple-output (MIMO) technique provides higher bit rates and better reliability in wireless systems. The efficient design of RF transceivers has a vital impact on the implementation of this technique. This first book is com- pletely devoted to RF transceiver design for MIMO communications. The book covers the most recent research in practical design and applications and can be an important resource for graduate students, wireless designers, and practical engineers.
標簽： Transceiver Design RF
上傳時間： 2020-06-01
上傳用戶：shancjb
Driven by the desire to boost the quality of service of wireless systems closer to that afforded by wireline systems, space-time processing for multiple-input multiple-output (MIMO) wireless communications research has drawn remarkable interest in recent years. Excit- ing theoretical advances, complemented by rapid transition of research results to industry products and services, have created a vibrant and growing area that is already established by all counts. This offers a good opportunity to reflect on key developments in the area during the past decade and also outline emerging trends.
標簽： Space-Time Processing
上傳時間： 2020-06-01
上傳用戶：shancjb
This effort started as an answer to the numerous questions the authors have repeatedly had to answer about electrostatic discharge (ESD) protection and input/output (1/0) designs. In the past no comprehensive book existed suffi- ciently covering these areas, and these topics were rarely taught in engineering schools. Thus first-time I/O and ESD protection designers have had consider- able trouble getting started. This book is in part an answer to such needs.
上傳時間： 2020-06-05
上傳用戶：shancjb
Recent work has shown that convolutional networks can be substantially deeper, more accurate, and efficient to train if they contain shorter connections between layers close to the input and those close to the output. In this paper, we embrace this observation and introduce the Dense Convo- lutional Network (DenseNet), which connects each layer to every other layer in a feed-forward fashion.
標簽： Convolutional Connected Networks Densely
上傳時間： 2020-06-10
上傳用戶：shancjb
lm75A溫度數(shù)字轉換器 FPGA讀寫實驗Verilog邏輯源碼Quartus工程文件+文檔資料,FPGA為CYCLONE4系列中的EP4CE6E22C8. 完整的工程文件，可以做為你的學習設計參考。LM75A 是一個使用了內置帶隙溫度傳感器和模數(shù)轉換技術的溫度數(shù)字轉換器。它也是一個溫度檢測器，可提供一個過熱檢測輸出。LM75A 包含許多數(shù)據(jù)寄存器：配置寄存器用來存儲器件的某些配置，如器件的工作模式、OS 工作模式、OS 極性和OS 故障隊列等（在功能描述一節(jié)中有詳細描述）；溫度寄存器（Temp），用來存儲讀取的數(shù)字溫度；設定點寄存器（Tos & Thyst），用來存儲可編程的過熱關斷和滯后限制，器件通過2 線的串行I2C 總線接口與控制器通信。LM75A 還包含一個開漏輸出（OS），當溫度超過編程限制的值時該輸出有效。LM75A 有3 個可選的邏輯地址管腳，使得同一總線上可同時連接8個器件而不發(fā)生地址沖突。LM75A 可配置成不同的工作條件。它可設置成在正常工作模式下周期性地對環(huán)境溫度進行監(jiān)控或進入關斷模式來將器件功耗降至最低。OS 輸出有2 種可選的工作模式：OS 比較器模式和OS 中斷模式。OS 輸出可選擇高電平或低電平有效。故障隊列和設定點限制可編程，為了激活OS 輸出，故障隊列定義了許多連續(xù)的故障。溫度寄存器通常存放著一個11 位的二進制數(shù)的補碼，用來實現(xiàn)0.125℃的精度。這個高精度在需要精確地測量溫度偏移或超出限制范圍的應用中非常有用。正常工作模式下，當器件上電時，OS 工作在比較器模式，溫度閾值為80℃，滯后75℃，這時，LM75A就可用作一個具有以上預定義溫度設定點的獨立的溫度控制器。module LM75_SEG_LED ( //input input sys_clk ,input sys_rst_n ,inout sda_port ,//output output wire seg_c1 ,output wire seg_c2 ,output wire seg_c3 ,output wire seg_c4 ,output reg seg_a ,output reg seg_b ,output reg seg_c ,output reg seg_e ,output reg seg_d ,output reg seg_f ,output reg seg_g ,output reg seg_h , output reg clk_sclk );//parameter define parameter WIDTH = 8;parameter SIZE = 8;//reg define reg [WIDTH-1:0] counter ;reg [9:0] counter_div ;reg clk_50k ;reg clk_200k ;reg sda ;reg enable ;
標簽： lm75a 數(shù)字轉換器 fpga verilog
上傳時間： 2021-10-27
上傳用戶：
FPGA采樣AD9238數(shù)據(jù)并通過VGA波形顯示例程 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。ADC 模塊型號為 AN9238，最大采樣率 65Mhz，精度為12 位。實驗中把 AN9238 的 2 路輸入以波形方式在 HDMI 上顯示出來，我們可以用更加直觀的方式觀察波形，是一個數(shù)字示波器雛形。module top( input clk, input rst_n, output ad9238_clk_ch0, output ad9238_clk_ch1, input[11:0] ad9238_data_ch0, input[11:0] ad9238_data_ch1, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue);wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire grid_hs;wire grid_vs;wire grid_de;wire[7:0] grid_r;wire[7:0] grid_g;wire[7:0] grid_b;wire wave0_hs;wire wave0_vs;wire wave0_de;wire[7:0] wave0_r;wire[7:0] wave0_g;wire[7:0] wave0_b;wire wave1_hs;wire wave1_vs;wire wave1_de;wire[7:0] wave1_r;wire[7:0] wave1_g;wire[7:0] wave1_b;wire adc_clk;wire adc0_buf_wr;wire[10:0] adc0_buf_addr;wire[7:0] adc0_bu
上傳時間： 2021-10-27
上傳用戶：qingfengchizhu
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實驗 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實驗簡介在前面的實驗中我們練習了 SD 卡讀寫，VGA 視頻顯示等例程，本實驗將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲器，再通過 VGA、LCD 等顯示。本實驗如果通過液晶屏顯示，需要有液晶屏模塊。2 實驗原理在前面的實驗中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內部產生的數(shù)據(jù)，本實驗將彩條替換為 SD 內的 BMP 圖片數(shù)據(jù)，但是 SD 卡讀取速度遠遠不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標簽： fpga
上傳時間： 2021-10-27
上傳用戶：
Research on microwave power amplififiers has gained a growing importance demanded by the many continuously developing applications which require such subsystem performance. A broad set of commercial and strategic systems in fact have their overall performance boosted by the power amplififier, the latter becoming an enabling component wherever its effificiency and output power actually allows functionalities and operating modes previously not possible. This is the case for the many wireless systems and battery-operated systems that form the substrate of everyday life, but also of high-performance satellite and dual-use systems.
上傳時間： 2021-10-30
上傳用戶：得之我幸78
