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A Computer-On-Module, or COM, is a Module with all components necessary for a bootable host computer, packaged as a super component. A COM requires a Carrier Board to bring out I/O and to power up. COMs are used to build single board computer solutions and offer OEMs fast time-to-market with reduced development cost. Like integrated circuits, they provide OEMs with significant freedom in meeting form-fit-function requirements. For all these reasons the COM methodology has gained much popularity with OEMs in the embedded industry. COM Express® is an open industry standard for Computer-On-Modules. It is designed to be future proof and to provide a smooth transition path from legacy Parallel interfaces to LVDS (Low Voltage Differential Signaling) interfaces. These include the PCI bus and Parallel ATA on the one hand and PCI Express and Serial ATA on the other hand.
標(biāo)簽：
PICMG_COM
COMe
上傳時間：
2013-11-05
上傳用戶：Wwill
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The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and Parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
標(biāo)簽：
314x
LPC
314
ARM
上傳時間：
2013-10-11
上傳用戶：yuchunhai1990
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The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and Parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
標(biāo)簽：
315x
LPC
315
ARM
上傳時間：
2014-01-17
上傳用戶：Altman
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中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively Parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽：
UltraScale
Xilinx
架構(gòu)
上傳時間：
2013-11-21
上傳用戶：wxqman
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本應(yīng)用指南講述一種實(shí)用的 MicroBlaze™ 系統(tǒng)，用于在非易失性 Platform Flash PROM 中存儲軟件代碼、用戶數(shù)據(jù)和配置數(shù)據(jù)，以簡化系統(tǒng)設(shè)計和降低成本。另外，本應(yīng)用指南還介紹一種可移植的硬件設(shè)計、一個軟件設(shè)計以及在實(shí)現(xiàn)流程中使用的其他腳本實(shí)用工具。
簡介許多 FPGA 設(shè)計都集成了使用 MicroBlaze 和 PowerPC™ 處理器的軟件嵌入式系統(tǒng)，這些設(shè)計同時使用外部易失性存儲器來執(zhí)行軟件代碼。使用易失性存儲器的系統(tǒng)還必須包含一個非易失性器件，用來在斷電期間存儲軟件代碼。大多數(shù) FPGA 系統(tǒng)都在電路板上使用 Platform FlashPROM (在本文中稱作 PROM)，用于在上電時加載 FPGA 配置數(shù)據(jù)。另外，許多應(yīng)用還可能使用其他非易失性器件(如 SPI Flash、Parallel Flash 或 PIC)來保存 MAC 地址等少量用戶數(shù)據(jù)，因此導(dǎo)致系統(tǒng)電路板上存在大量非易失性器件。
標(biāo)簽：
MicroBlaze
Platform
Flash
XAPP
上傳時間：
2013-10-15
上傳用戶：rocwangdp
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為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對移相（QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計要求。
Abstract:
In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/Parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and Parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽：
QDPSK
CPLD
調(diào)制解調(diào)
電路設(shè)計
上傳時間：
2013-10-28
上傳用戶：jyycc
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The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The Parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。
Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM.
The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
標(biāo)簽：
賽靈思
電機(jī)控制
開發(fā)套件
英文
上傳時間：
2013-10-28
上傳用戶：wujijunshi
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Altera recommends the following system configuration: * Pentium II 400 with 512-MB system memory (faster systems give better software performance) * SVGA monitor * CD-ROM drive * One or more of the following I/O ports: - USB port (if using Windows XP or Windows 2000) for USB-Blaster(TM) or MasterBlaster(TM) communications cables, or APU programming unit - Parallel port for ByteBlasterMV(TM) or ByteBlaster(TM) II download cables - Serial port for MasterBlaster communications cable * TCP/IP networking protocol installed * Windows 2000, Windows NT 4.0 with Service Pack 3 or later, or Windows XP * Internet Explorer 5.0 or later Memory & Disk Space Requirements USB開發(fā)
標(biāo)簽：
system
configuration
recommends
following
上傳時間：
2015-03-27
上傳用戶：13188549192
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This toolbox distributes processes over matlab workers available over the intranet/internet (SPMD or MPMD Parallel model). It is very useful for corsely granular Parallelization problems and in the precesence of a distributed and heterogeneus computer enviroment. No need for configuration files ! Cross platforms, cross OS and cross MATLAB versions. Workers can be added to the Parallel computation even if it has started. No need of a common file system, all comms are using tcpip connections
標(biāo)簽：
over
distributes
available
processes
上傳時間：
2014-01-03
上傳用戶：希醬大魔王
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Micro In-System Programmer Brief Installation Notes
Enter the src directory.
If uisp does not compile successfully, add switch -DNO_DIRECT_IO in the
Makefile to remove support for direct I/O port access (that may be
necessary on non-PC architectures). Parallel port access should still
work if you have the Linux ppdev driver (patch for 2.2.17 is in the
kernel directory, ppdev is standard in 2.4 kernels). Please lobby
Alan Cox to include this tiny little driver in 2.2.x too :).
To make it type:
make
and to install it:
make install
If you have any further doubts, please consult UISP s homepage:
http://www.nongnu.org/uisp/
標(biāo)簽：
Installation
Programmer
In-System
directory
上傳時間：
2013-12-23
上傳用戶：小儒尼尼奧
