This file is a function under matlab which allow to compute and plot fast fourier transform of a signal. We can observe the effect of the signal Parameter can be changed such as frequency and N points.
標簽： transform function compute fourier
上傳時間： 2017-06-27
上傳用戶：米卡
optailpiduse of the model reference adaptive control method! Lypanuov stability theory used to design Parameter adjustment
標簽： optailpiduse reference stability adaptive
上傳時間： 2014-01-26
上傳用戶：13215175592
The function applies the Madsen method for Doppler Centroid estimation. The input are: 1) the raw data, the Parameter of the distance between samples in azimuth to be correlated and the PRF (Pulse repetition frequency)
標簽： estimation The the Centroid
上傳時間： 2017-08-12
上傳用戶：pinksun9
sba, a C/C++ package for generic sparse bundle adjustment is almost invariably used as the last step of every feature-based multiple view reconstruction vision algorithm to obtain optimal 3D structure and motion (i.e. camera matrix) Parameter estimates. Provided with initial estimates, BA simultaneously refines motion and structure by minimizing the reprojection error between the observed and predicted image points.
標簽： adjustment invariably package generic
上傳時間： 2013-12-18
上傳用戶：xsnjzljj
Computational models are commonly used in engineering design and scientific discovery activities for simulating complex physical systems in disciplines such as fluid mechanics, structural dynamics, heat transfer, nonlinear structural mechanics, shock physics, and many others. These simulators can be an enormous aid to engineers who want to develop an understanding and/or predictive capability for complex behaviors typically observed in the corresponding physical systems. Simulators often serve as virtual prototypes, where a set of predefined system Parameters, such as size or location dimensions and material properties, are adjusted to improve the performance of a system, as defined by one or more system performance objectives. Such optimization or tuning of the virtual prototype requires executing the simulator, evaluating performance objective(s), and adjusting the system Parameters in an iterative, automated, and directed way. System performance objectives can be formulated, for example, to minimize weight, cost, or defects; to limit a critical temperature, stress, or vibration response; or to maximize performance, reliability, throughput, agility, or design robustness. In addition, one would often like to design computer experiments, run Parameter studies, or perform uncertainty quantification (UQ). These approaches reveal how system performance changes as a design or uncertain input variable changes. Sampling methods are often used in uncertainty quantification to calculate a distribution on system performance measures, and to understand which uncertain inputs contribute most to the variance of the outputs. A primary goal for Dakota development is to provide engineers and other disciplinary scientists with a systematic and rapid means to obtain improved or optimal designs or understand sensitivity or uncertainty using simulationbased models. These capabilities generally lead to improved designs and system performance in earlier design stages, alleviating dependence on physical prototypes and testing, shortening design cycles, and reducing product development costs. In addition to providing this practical environment for answering system performance questions, the Dakota toolkit provides an extensible platform for the research and rapid prototyping of customized methods and meta-algorithms
標簽： Optimization and Uncertainty Quantification
上傳時間： 2016-04-08
上傳用戶：huhu123456
lm75A溫度數字轉換器 FPGA讀寫實驗Verilog邏輯源碼Quartus工程文件+文檔資料,FPGA為CYCLONE4系列中的EP4CE6E22C8. 完整的工程文件，可以做為你的學習設計參考。LM75A 是一個使用了內置帶隙溫度傳感器和模數轉換技術的溫度數字轉換器。它也是一個溫度檢測器，可提供一個過熱檢測輸出。LM75A 包含許多數據寄存器：配置寄存器用來存儲器件的某些配置，如器件的工作模式、OS 工作模式、OS 極性和OS 故障隊列等（在功能描述一節中有詳細描述）；溫度寄存器（Temp），用來存儲讀取的數字溫度；設定點寄存器（Tos & Thyst），用來存儲可編程的過熱關斷和滯后限制，器件通過2 線的串行I2C 總線接口與控制器通信。LM75A 還包含一個開漏輸出（OS），當溫度超過編程限制的值時該輸出有效。LM75A 有3 個可選的邏輯地址管腳，使得同一總線上可同時連接8個器件而不發生地址沖突。LM75A 可配置成不同的工作條件。它可設置成在正常工作模式下周期性地對環境溫度進行監控或進入關斷模式來將器件功耗降至最低。OS 輸出有2 種可選的工作模式：OS 比較器模式和OS 中斷模式。OS 輸出可選擇高電平或低電平有效。故障隊列和設定點限制可編程，為了激活OS 輸出，故障隊列定義了許多連續的故障。溫度寄存器通常存放著一個11 位的二進制數的補碼，用來實現0.125℃的精度。這個高精度在需要精確地測量溫度偏移或超出限制范圍的應用中非常有用。正常工作模式下，當器件上電時，OS 工作在比較器模式，溫度閾值為80℃，滯后75℃，這時，LM75A就可用作一個具有以上預定義溫度設定點的獨立的溫度控制器。module LM75_SEG_LED ( //input input sys_clk ,input sys_rst_n ,inout sda_port ,//output output wire seg_c1 ,output wire seg_c2 ,output wire seg_c3 ,output wire seg_c4 ,output reg seg_a ,output reg seg_b ,output reg seg_c ,output reg seg_e ,output reg seg_d ,output reg seg_f ,output reg seg_g ,output reg seg_h , output reg clk_sclk );//Parameter define Parameter WIDTH = 8;Parameter SIZE = 8;//reg define reg [WIDTH-1:0] counter ;reg [9:0] counter_div ;reg clk_50k ;reg clk_200k ;reg sda ;reg enable ;
上傳時間： 2021-10-27
上傳用戶：
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實驗 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實驗簡介在前面的實驗中我們練習了 SD 卡讀寫，VGA 視頻顯示等例程，本實驗將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲器，再通過 VGA、LCD 等顯示。本實驗如果通過液晶屏顯示，需要有液晶屏模塊。2 實驗原理在前面的實驗中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內部產生的數據，本實驗將彩條替換為 SD 內的 BMP 圖片數據，但是 SD 卡讀取速度遠遠不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);Parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthParameter ADDR_BITS = 24
標簽： fpga
上傳時間： 2021-10-27
上傳用戶：
IIC接口E2PROM(AT24C64) 讀寫VERILOG 驅動源碼+仿真激勵文件:module i2c_dri #( Parameter SLAVE_ADDR = 7'b1010000 , //EEPROM從機地址 Parameter CLK_FREQ = 26'd50_000_000, //模塊輸入的時鐘頻率 Parameter I2C_FREQ = 18'd250_000 //IIC_SCL的時鐘頻率 ) ( input clk , input rst_n , //i2c interface input i2c_exec , //I2C觸發執行信號 input bit_ctrl , //字地址位控制(16b/8b) input i2c_rh_wl , //I2C讀寫控制信號 input [15:0] i2c_addr , //I2C器件內地址 input [ 7:0] i2c_data_w , //I2C要寫的數據 output reg [ 7:0] i2c_data_r , //I2C讀出的數據 output reg i2c_done , //I2C一次操作完成 output reg i2c_ack , //I2C應答標志 0:應答 1:未應答 output reg scl , //I2C的SCL時鐘信號 inout sda , //I2C的SDA信號 //user interface output reg dri_clk //驅動I2C操作的驅動時鐘 );//localparam definelocalparam st_idle = 8'b0000_0001; //空閑狀態localparam st_sladdr = 8'b0000_0010; //發送器件地址(slave address)localparam st_addr16 = 8'b0000_0100; //發送16位字地址localparam st_addr8 = 8'b0000_1000; //發送8位字地址localparam st_data_wr = 8'b0001_0000; //寫數據(8 bit)localparam st_addr_rd = 8'b0010_0000; //發送器件地址讀localparam st_data_rd = 8'b0100_0000; //讀數據(8 bit)localparam st_stop = 8'b1000_0000; //結束I2C操作//reg definereg sda_dir ; //I2C數據(SDA)方向控制reg sda_out ; //SDA輸出信號reg st_done ; //狀態結束reg wr_flag ; //寫標志reg [ 6:0] cnt ; //計數reg [ 7:0] cur_state ; //狀態機當前狀態reg [ 7:0] next_state; //狀態機下一狀態reg [15:0] addr_t ; //地址reg [ 7:0] data_r ; //讀取的數據reg [ 7:0] data_wr_t ; //I2C需寫的數據的臨時寄存reg [ 9:0] clk_cnt ; //分頻時
標簽： iic 接口 e2prom at24c64 verilog 驅動 仿真
上傳時間： 2021-11-05
上傳用戶：
基于FPGA設計的sdram讀寫測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號,容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數據寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號都是時鐘信號。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);Parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthParameter ADDR_BITS = 24 ; //external memory user interface address widthParameter BUSRT_BITS = 10 ; //external memory user interface burst widthParameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標簽： fpga sdram verilog quartus
上傳時間： 2021-12-18
上傳用戶：
ADS8329 Verilog fpga 驅動源碼，2.7V 至 5.5V 16 位 1MSPS 串行模數轉換器 ADC芯片ADS8329數據采集的verilog代碼，已經用在工程中，可以做為你的設計參考。( input clock, input timer_clk_r, input reset, output reg sample_over, output reg ad_convn, input ad_eocn, output reg ad_csn, output reg ad_clk, input ad_dout, output reg ad_din, output reg [15:0] ad_data_lock);reg [15:0] ad_data_old;reg [15:0] ad_data_new; reg [19:0] ad_data_temp; reg [15:0] ad_data;reg [4:0] ad_data_cnt;reg [4:0] ad_spi_cnt; reg [5:0] time_dly_cnt; Parameter [3:0] state_mac_IDLE = 0, state_mac_0 = 1, state_mac_1 = 2, state_mac_2 = 3, state_mac_3 = 4, state_mac_4 = 5, state_mac_5 = 6, state_mac_6 = 7, state_mac_7 = 8, state_mac_8 = 9, state_mac_9 = 10, state_mac_10 = 11, state_mac_11 = 12, state_mac_12 = 13, state_mac_13 = 14, state_mac_14 = 15; reg [3:0] state_curr;reg [3:0] state_next;
上傳時間： 2022-01-30
上傳用戶：1208020161
