The following is a list of MATLAB codes which includes the radar absorbing material design, the antenna pattern, the observation points generation, and the amplitude error and phase error calculations.
標(biāo)簽： following absorbing the includes
上傳時間： 2014-01-04
上傳用戶：l254587896
DDR SDRAM控制器的VHDL源代碼，含詳細(xì)設(shè)計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
計算全息close all clc clear A=zeros(64) A(15:20,20:40)=1 A(15:50,20:25)=1 A(45:50,20:40)=1 A(30:34,20:35)=1 ％ ppp=exp(rand(64)*pi*2*i) A=A.*ppp ％ Author s email: zjliu2001@163.com figure imshow(abs(A),[]) Fa=fft2(fftshift(A)) Fs=fftshift(Fa) Am=abs(Fs) ％ amplitude Ph=angle(Fs) ％ phase s=11 ％ 這表示邊長嗎？ cgh=zeros(64*s) th=max(max(abs(Fs)))
標(biāo)簽： 20 close clear zeros
上傳時間： 2014-10-13
上傳用戶：wweqas
This is GPS Acquisition..by Matlab, this file performs cold start acquisition on the collected "data". It searches for GPS signals of all satellites, which are listed in field "acqSatelliteList" in the settings structure. Function saves code phase and frequency of the detected signals in the "acqResults" structure.
標(biāo)簽： Acquisition acquisition collected performs
上傳時間： 2013-12-28
上傳用戶：wxhwjf
This is GPS Matlab acquisition code. Function performs cold start acquisition on the collected "data". It searches for GPS signals of all satellites, which are listed in field "acqSatelliteList" in the settings structure. Function saves code phase and frequency of the detected signals in the "acqResults" structure.
標(biāo)簽： acquisition collected Function performs
上傳時間： 2014-08-07
上傳用戶：xjz632
Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt generation. As with the SPI found in MC68HC11 processors the core features programmable clock phase [CPHA] and clock polarity [CPOL]. The core features an 8bit wishbone interface. Very simple, very small.
標(biāo)簽： Peripheral Interface available Enhanced
上傳時間： 2014-12-06
上傳用戶：invtnewer
This the Firmware code for the ADE7758 for the PIC Micro controller for the computation of three phase parameters.
標(biāo)簽： the for computation controller
上傳時間： 2017-04-01
上傳用戶：lanwei
MATLAB-based program that generates plots of input power and shaft torque for variable-frequency operation of three-phase induction motors
標(biāo)簽： variable-frequency MATLAB-based generates program
上傳時間： 2017-04-22
上傳用戶：ma1301115706
The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented. The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940). The design is fully pipelined for maximum throughput.
標(biāo)簽： e.g. communication Transform important
上傳時間： 2017-06-25
上傳用戶：gxf2016
The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, submicron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution.
標(biāo)簽： application real-time Synopsys emphasis
上傳時間： 2017-07-05
上傳用戶：waitingfy
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