* "Copyright (c) 2006 Robert B. Reese ("AUTHOR")"
* All rights reserved.
* (R. Reese, reese@ece.msstate.edu, Mississippi State University)
* IN NO EVENT SHALL THE "AUTHOR" BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE "AUTHOR"
* HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
This example application is a collection of Flash Lite do s and don ts from the
usability point of view. The application contains real examples and animations
of static examples that help you to see problematic issues in real life on a
Nokia device. The application is optimized for devices with the resolution 170 x 208
pixels used in portrait mode.
This example application is closely related to the document Flash Lite: Visual Guide,
and it is highly recommended to read the document before going through this example.
Verilog HDL: Magnitude
For a vector (a,b), the magnitude representation is the following:
A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm.
design LP,HP,B S digital Butterworth and Chebyshev
filter. All array has been specified internally,so user only need to
input f1,f2,f3,f4,fs(in hz), alpha1,alpha2(in db) and iband (to specify
the type of to design). This program output hk(z)=bk(z)/ak(z),k=1,2,...,
ksection and the freq.
About:
hamsterdb is a database engine written in ANSI C. It supports a B+Tree index structure, uses memory mapped I/O (if available), supports cursors, and can create in-memory databases.
Release focus: Major feature enhancements
Changes:
This release comes with many changes and new features. It can manage multiple databases in one file. A new flag (HAM_LOCK_EXCLUSIVE) places an exclusive lock on the file. hamsterdb was ported to Windows CE, and the Solution file for Visual Studio 2005 now supports builds for x64. Several minor bugs were fixed, performance was improved, and small API changes occurred. Pre-built libraries for Windows (32-bit and 64-bit) are available for download.
Author:
cruppstahl
Floyd-Warshall算法描述
1)適用范圍：
a)APSP(All Pairs Shortest Paths)
b)稠密圖效果最佳
c)邊權可正可負
2)算法描述：
a)初始化：dis[u,v]=w[u,v]
b)For k:=1 to n
For i:=1 to n
For j:=1 to n
If dis[i,j]>dis[i,k]+dis[k,j] Then
Dis[I,j]:=dis[I,k]+dis[k,j]
c)算法結束：dis即為所有點對的最短路徑矩陣
3)算法小結：此算法簡單有效，由于三重循環結構緊湊，對于稠密圖，效率要高于執行|V|次Dijkstra算法。時間復雜度O(n^3)。
考慮下列變形：如(I,j)∈E則dis[I,j]初始為1,else初始為0，這樣的Floyd算法最后的最短路徑矩陣即成為一個判斷I,j是否有通路的矩陣。更簡單的，我們可以把dis設成boolean類型，則每次可以用“dis[I,j]:=dis[I,j]or(dis[I,k]and dis[k,j])”來代替算法描述中的藍色部分，可以更直觀地得到I,j的連通情況。
NAME: u2440mon.c
DESC: u2440mon entry point,menu,download
HISTORY:
Mar.25.2002:purnnamu: S3C2400X profile.c is ported for S3C2410X.
Mar.27.2002:purnnamu: DMA is enabled.
Apr.01.2002:purnnamu: isDownloadReady flag is added.
Apr.10.2002:purnnamu: - Selecting menu is available in the waiting loop.
So, isDownloadReady flag gets not needed
- UART ch.1 can be selected for the console.
Aug.20.2002:purnnamu: revision number change 0.2 -> R1.1
Sep.03.2002:purnnamu: To remove the power noise in the USB signal, the unused CLKOUT0,1 is disabled.
The FastICA package is a free (GPL) MATLAB program that implements the fast fixed-point algorithm for independent component analysis and projection pursuit. It features an easy-to-use graphical user interface, and a computationally powerful algorithm.
For developers using FPGAs for the
implementation of floating-point DSP
functions, one key challenge is how to
decompose the computation algorithm
into sequences of parallel hardware
processes while efficiently managing data flow through the parallel pipelines of these processes.
