This is the Xilinx Dual Processor Reference Designs suite. The designs illustrate a few differentdual-core architectures based on the MicroBlaze™ and PowerPC™ Processors. The designsillustrate various concepts described in the Xilinx White Paper WP262 titled, “DesigningMultiProcessor Systems in Platform Studio”. There are simple software applications includedwith the reference designs that show various forms of interaction between the two Processors.
標(biāo)簽： XAPP 996 雙處理器 參考設(shè)計
上傳時間： 2013-10-29
上傳用戶：旭521
With the Altera Nios II embedded Processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II Processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II Processor
上傳時間： 2013-11-07
上傳用戶：swing
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point Processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coProcessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時間： 2013-10-28
上傳用戶：15501536189
Today in many applications such as network switches, routers, multi-computers,and Processor-memory interfaces, the ability to integrate hundreds of multi-gigabit I/Os is desired to make better use of the rapidly advancing IC technology.
上傳時間： 2013-10-30
上傳用戶：ysjing
摘要：介紹了基于數(shù)字信號處理(Digital Signal Processor,DSP)的運動控制器GT-800在貼片機控制系統(tǒng)中的應(yīng)用。該系統(tǒng)采用以PC機為上位機、GT-800運動控制器為下位機的硬件結(jié)構(gòu)，上下位機之間的通訊采用基于ISA總線的雙端口RAM的模式，系統(tǒng)的軟件設(shè)計采用基于VisualC++6．0的軟件設(shè)計模式。關(guān)鍵詞：GT-800運動控制器；貼片機；運動控制；機器視覺
標(biāo)簽： 800 GT 貼片機 控制系統(tǒng)
上傳時間： 2013-10-18
上傳用戶：asdkin
通過以太網(wǎng)遠(yuǎn)程配置Nios II 處理器 應(yīng)用筆記 Firmware in embedded hardware systems is frequently updated over the Ethernet. For embedded systems that comprise a discrete microProcessor and the devices it controls, the firmware is the software image run by the microProcessor. When the embedded system includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If the FPGA includes a Nios® II soft Processor, you can upgrade both the Nios II Processor—as part of the FPGA image—and the software that the Nios II Processor runs, in a single remote configuration session.
標(biāo)簽： Nios 遠(yuǎn)程 處理器 應(yīng)用筆記
上傳時間： 2013-11-22
上傳用戶：chaisz
面向Eclips的Nios II軟件構(gòu)建工具手冊 The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the Eclipse™ framework and the Eclipse C/C++ development toolkit (CDT) plugins. The Nios II SBT for Eclipse provides a consistent development platform that works for all Nios II embedded Processor systems. You can accomplish all Nios II software development tasks within Eclipse, including creating, editing, building, running, debugging, and profiling programs.
上傳時間： 2013-11-02
上傳用戶：瓦力瓦力hong
使用Nios II緊耦合存儲器教程 Chapter 1. Using Tightly Coupled Memory with the Nios II Processor Reasons for Using Tightly Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . 1–1 Tradeoffs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Guidelines for Using Tightly Coupled Memory . . . .. . . . . . . . 1–2 Hardware Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 Software Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . 1–3 Locating Functions in Tightly Coupled Memory . . . . . . . . . . . . . 1–3 Tightly Coupled Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4 Dual Port Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . 1–5 Building a Nios II System with Tightly Coupled Memory . . . . . . . . . . . 1–5
上傳時間： 2013-10-13
上傳用戶：黃婷婷思密達(dá)
Nios II 軟件開發(fā)人員手冊中的緩存和緊耦合存儲器部分 Nios® II embedded Processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II Processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II architecture provides facilities to perform the following actions:
上傳時間： 2013-10-25
上傳用戶：蟲蟲蟲蟲蟲蟲
Nios II定制指令用戶指南：With the Altera Nios II embedded Processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II Processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II Processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時間： 2013-10-12
上傳用戶：kang1923
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