Nios II 系列處理器配置選項(xiàng):This chapter describes the Nios® II Processor parameter editor in Qsys and SOPC Builder. The Nios II Processor parameter editor allows you to specify the Processor features for a particular Nios II hardware system. This chapter covers the features of the Nios II Processor that you can configure with the Nios II Processor parameter editor; it is not a user guide for creating complete Nios II Processor systems.
上傳時(shí)間： 2015-01-01
上傳用戶：mahone
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither Processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
標(biāo)簽： Spartan XAPP FPGA 098
上傳時(shí)間： 2013-11-01
上傳用戶：wojiaohs
The introduction of Spartan-3™ devices has createdmultiple changes in the evolution of embedded controldesigns and pushed processing capabilities to the “almostfreestage.” With these new FPGAs falling under $20, involume, with over 1 million system gates, and under $5for 100K gate-level units, any design with programmablelogic has a readily available 8- or 16-bit Processor costingless than 75 cents and 32-bit Processor for less than $1.50.
上傳時(shí)間： 2013-10-21
上傳用戶：ligi201200
The Virtex™-4 user access register (USR_ACCESS_VIRTEX4) is a 32-bit register thatprovides direct access to bitstream data by the FPGA fabric. It is useful for loadingPowerPC™ 405 (PPC405) Processor caches and/or other data into the FPGA after the FPGAhas been configured, thus achieving partial reconfiguration. The USR_ACCESS_VIRTEX4register is programmed through the bitstream with a command that writes a series of 32-bitwords.
標(biāo)簽： USR_ACCESS PowerPC XAPP 719
上傳時(shí)間： 2013-12-23
上傳用戶：yuanwenjiao
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
上傳時(shí)間： 2013-10-27
上傳用戶：Breathe0125
The PPC405 Virtex-4 is a wrapper around the Virtex-4PowerPC™ 405 Processor Block primitive. For detailsregarding the PowerPC 405, see the PowerPC 405 ProcessorBlock Reference Guide.
標(biāo)簽： Wrapper Virtex 306 405
上傳時(shí)間： 2015-01-02
上傳用戶：JIUSHICHEN
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ Processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
WP369可擴(kuò)展式處理平臺(tái)-各種嵌入式系統(tǒng)的理想解決方案 ：Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore Processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a Processor-centric approach by defining a comprehensive Processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
標(biāo)簽： 369 WP 擴(kuò)展式 處理平臺(tái)
上傳時(shí)間： 2013-10-18
上傳用戶：cursor
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMProcessor-based system with Xilinx 28nm programmable logic—in a single device. The Processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
標(biāo)簽： xilinx Zynq 7000 EPP
上傳時(shí)間： 2013-10-09
上傳用戶：evil
研究一種基于TMS320F28335 DSP（Digital Signal Processor）的全數(shù)字飛行器控制系統(tǒng)的硬件設(shè)計(jì)，分析了其結(jié)構(gòu)組成：主控制器電路、舵面位置檢測(cè)電路和通訊等硬件電路設(shè)計(jì)。經(jīng)過(guò)多次試驗(yàn)調(diào)試，所設(shè)計(jì)的硬件系統(tǒng)可以滿足飛行器性能要求。
標(biāo)簽： 飛行器 舵機(jī) 控制系統(tǒng) 硬件設(shè)計(jì)
上傳時(shí)間： 2013-10-10
上傳用戶：z1191176801
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