為了在CDMA系統中更好地應用QDPSK數字調制方式，在分析四相相對移相（QDPSK)信號調制解調原理的基礎上，設計了一種QDPSK調制解調電路，它包括串并轉換、差分編碼、四相載波產生和選相、相干解調、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中，測試結果表明，調制電路能正確選相，解調電路輸出數據與QDPSK調制輸入數據完全一致，達到了預期的設計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test RESULT shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上傳時間： 2013-10-28
上傳用戶：jyycc
The revolution of automation on factory floors is a key driver for the seemingly insatiable demand for higher productivity， lower total cost of ownership，and high safety. As a RESULT， industrial applications drive an insatiable demand of higher data bandwidth and higher system-level performance. This white paper describes the trends and challenges seen by designers and how FPGAs enable solutions to meet their stringent design goals.
上傳時間： 2013-11-08
上傳用戶：yan2267246
基于通用集成運算放大器，利用MASON公式設計了一個多功能二階通用濾波器，能同時或分別實現低通、高通和帶通濾波，也能設計成一個正交振蕩器。電路的極點頻率和品質因數能夠獨立、精確地調節。電路使用4個集成運放、2個電容和11個電阻，所有集成運放的反相端虛地。利用計算機仿真電路的通用濾波功能、極點頻率和品質因數的獨立控制和正交正弦振蕩，從而證明該濾波器正確有效。 Abstract: A new multifunctional second-order filter based on OPs was presented by MASON formula. Functions， such as high-pass， band-pass， low-pass filtering， can be realized respectively and simultaneously， and can become a quadrature oscillator by modifying resistance ratio. Its pole angular frequency and quality factor can be tuned accurately and independently. The circuit presented contains four OPs， two capacitors， and eleven resistances， and inverting input of all OPs is virtual ground. Its general filtering， the independent control of pole frequency and quality factor and quadrature sinusoidal oscillation were simulated by computer， and the RESULT shows that the presented circuit is valid and effective.
上傳時間： 2013-10-09
上傳用戶：13788529953
編程查找指定目錄下所有EXE文件，并將其全路徑存入RESULT.txt中，要求用遞歸
上傳時間： 2014-01-11
上傳用戶：1051290259
A Waiter relays an order Object to a Producer, waits in an independent thread during the production, and then delivers the RESULT using a Consumer callback method.
標簽： independent production Producer Waiter
上傳時間： 2015-02-10
上傳用戶：lepoke
首先，打開圖像（256色）；再次，進行歸一化處理，點擊“一次性處理”；最后，點擊“R”或者使用菜單找到相應項來進行識別。識別的結果顯示在屏幕上，同時也輸出到文件RESULT.txt中。
標簽：
上傳時間： 2013-12-23
上傳用戶：851197153
This example program shows how to configure and use the A/D Converter of the following microcontroller: STMicroelectronics ST10F166 After configuring the A/D, the program reads the A/D RESULT and outputs the converted value using the serial port. To run this program... Build the project (Project Menu, Build Target) Start the debugger (Debug Menu, Start/Stop Debug Session) View the Serial Window (View Menu, Serial Window #1) View the A/D converter peripheral (Peripheral Menu, A/D Converter) Run the program (Debug Menu, Go) A debug script (debug.ini) creates buttons that set different analog values in A/D channels. As the program runs, you will see the A/D input and output change. Other buttons create signals that generate sine wave or sawtooth patterns as analog inputs. µ Vision3 users may enable the built-in Logic Analyzer to view, measure and compare these input signals graphically.
標簽： microcontroll Converter configure following
上傳時間： 2014-12-01
上傳用戶：獨孤求源
VHDL 關于2DFFT設計程序 u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be seen in the following section. u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus network, and it support these sub-modules scinode1∼ scinode9 reset and clk and global_cnt signals to synchronous the sub-modules to simplify the overall design. u proj2.wfc: VSS simulation RESULT that is the same as the ModelSim simulation RESULT. u Pro2_2.wfc: VSS simulation RESULT of another test pattern can’t cause overflow situation.
標簽： scinode1 scinode details 2DFFT
上傳時間： 2014-12-02
上傳用戶：15071087253
AVL Tree implementation: I also included a test function to compare the AVL Tree performance with STL Set and Map. Compile the source mavltree.cpp and run it to see the RESULT!
標簽： Tree implementation performance AVL
上傳時間： 2013-12-19
上傳用戶：3到15
A method is presented for augmenting an extended Kalman filter with an adaptive element. The RESULTing estimator provides robustness to parameter uncertainty and unmodeled dynamics.
標簽： augmenting presented adaptive extended
上傳時間： 2014-01-05
上傳用戶：qq1604324866
