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Real-Time-Clock

  • LTC1099基于PC的數(shù)據(jù)采集板實現(xiàn)

    A complete design for a data acquisition card for the IBM PC is detailed in this application note. Additionally, C language code is provided to allow sampling of data at speed of more than 20kHz. The speed limitation is strictly based on the execution speed of the "C" data acquisition loop. A "Turbo" XT can acquire data at speeds greater than 20kHz. Machines with 80286 and 80386 processors can go faster than 20kHz. The computer that was used as a test bed in this application was an XT running at 4.77MHz and therefore all system timing and acquisition time measurements are based on a 4.77MHz clock speed.

    標簽: 1099 LTC 數(shù)據(jù) 采集板

    上傳時間: 2013-10-29

    上傳用戶:BOBOniu

  • 使用時鐘PLL的源同步系統(tǒng)時序分析

    使用時鐘PLL的源同步系統(tǒng)時序分析一)回顧源同步時序計算Setup Margin = Min Clock Etch Delay – Max Data Etch Delay – Max Delay Skew – Setup TimeHold Margin = Min Data Etch Delay – Max Clock Etch Delay + Min Delay Skew + Data Rate – Hold Time下面解釋以上公式中各參數(shù)的意義:Etch Delay:與常說的飛行時間(Flight Time)意義相同,其值并不是從仿真直接得到,而是通過仿真結(jié)果的后處理得來。請看下面圖示:圖一為實際電路,激勵源從輸出端,經(jīng)過互連到達接收端,傳輸延時如圖示Rmin,Rmax,F(xiàn)min,F(xiàn)max。圖二為對應輸出端的測試負載電路,測試負載延時如圖示Rising,F(xiàn)alling。通過這兩組值就可以計算得到Etch Delay 的最大和最小值。

    標簽: PLL 時鐘 同步系統(tǒng) 時序分析

    上傳時間: 2013-11-05

    上傳用戶:VRMMO

  • 基于RTW的三電平雙PWM變換器控制系統(tǒng)設(shè)計

    此提出了一種基于Matlab/Simulink及實時代碼生成工具R哪(Real.Time Workshop)的電力電子與電力傳動控制系統(tǒng)軟件的設(shè)計方法。首先在Simulink下搭建控制系統(tǒng)模型,進行相應仿真完善,驗證控制算法,根據(jù)目標DSP型號添加相應DSP內(nèi)核、外設(shè)并設(shè)置控制參數(shù),然后直接將模型轉(zhuǎn)化為相應DSP的C源代碼.在相應的硬件平臺支持下即可完成相關(guān)實驗。

    標簽: RTW PWM 三電平 變換器控制

    上傳時間: 2013-11-04

    上傳用戶:wincoder

  • 100-15V TO 12V DCDC 原理圖 PCB BOM表

    高的工作電壓高達100V N雙N溝道MOSFET同步驅(qū)動 The D810DCDC is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 100V, making it ideal for telecom and automotive applications. The D810DCDC uses a constant on-time valley current control architecture to deliver very low duty cycles with accurate cycle-by-cycle current limit, without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bandwidth (25MHz) error amplifi er provides very fast line and load transient response. Large 1Ω gate drivers allow the D810DCDC to drive multiple MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN and can also be synchronized to an external clock for switching-noise sensitive applications. Integrated bias control generates gate drive power from the input supply during start-up and when an output shortcircuit occurs, with the addition of a small external SOT23 MOSFET. When in regulation, power is derived from the output for higher effi ciency.

    標簽: DCDC 100 12V BOM

    上傳時間: 2013-10-24

    上傳用戶:wd450412225

  • MAXX9257 MAX9258芯片可編程SerDes持續(xù)時間計算

    The MAX9257/MAX9258 programmable serializer/deserializer (SerDes) devices transfer both video data and control signals over the same twisted-pair cable. However, control data can only be transmitted during the vertical blank time, which is indicated by the control-channel-enabled output (CCEN) signal. The electronic control unit (ECU) firmware designer needs to know how quickly to respond to the CCEN signal before it times out and how to calculate this duration. This application note describes how to calculate the duration of the CCEN for the MAX9257/MAX9258 SerDes chipset. The calculation is based on STO timeout, clock frequency, and UART bit timing. The CCEN duration is programmable and can be closed if not in use.

    標簽: SerDes MAXX 9257 9258

    上傳時間: 2014-01-24

    上傳用戶:xingisme

  • HT47R20A-1時基(Time Base)使用介紹

    HT47R20A-1時基(Time Base)使用介紹 HT47 系列單片機的時基可提供一個周期性超時時間周期以產(chǎn)生規(guī)則性的內(nèi)部中斷。時基的時鐘來源可由掩膜選擇設(shè)定為WDT 時鐘、RTC 時鐘或指令時鐘(系統(tǒng)時鐘/4);其超時時間范圍可由掩膜選擇設(shè)定為“時鐘來源”/212~“時鐘來源”/215。如果時基發(fā)生超時現(xiàn)象,則其對應的中斷請求標志(TBF)會被置位,如果中斷允許,則產(chǎn)生一個中斷服務到08H 的地址。

    標簽: Base Time HT 47

    上傳時間: 2013-11-15

    上傳用戶:13925096126

  • Input Signal Rise and Fall Tim

    All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.

    標簽: Signal Input Fall Rise

    上傳時間: 2013-10-23

    上傳用戶:copu

  • 介紹C16x系列微控制器的輸入信號升降時序圖及特性

    All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.

    標簽: C16x 微控制器 輸入信號 時序圖

    上傳時間: 2014-04-02

    上傳用戶:han_zh

  • 用單片機配置FPGA—PLD設(shè)計技巧

    用單片機配置FPGA—PLD設(shè)計技巧 Configuration/Program Method for Altera Device Configure the FLEX Device You can use any Micro-Controller to configure the FLEX device–the main idea is clocking in ONE BITof configuration data per CLOCK–start from the BIT 0􀂄The total Configuration time–e.g. 10K10 need 15K byte configuration file•calculation equation–10K10* 1.5= 15Kbyte–configuration time for the file itself•15*1024*8*clock = 122,880Clock•assume the CLOCK is 4MHz•122,880*1/4Mhz=30.72msec

    標簽: FPGA PLD 用單片機 設(shè)計技巧

    上傳時間: 2013-10-09

    上傳用戶:a67818601

  • Backpropagation Network Time-Series Forecasting 源碼, 經(jīng)典的BPN人工神經(jīng)網(wǎng)絡(luò)例子源碼

    Backpropagation Network Time-Series Forecasting 源碼, 經(jīng)典的BPN人工神經(jīng)網(wǎng)絡(luò)例子源碼

    標簽: Backpropagation Forecasting Time-Series Network

    上傳時間: 2015-01-05

    上傳用戶:tb_6877751

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