RS232.C was written to provide all of the basic functionality needed to employ serial I/O in any application written with Borland C language compilers. Some features are: 1. Ease of use. No assembly language or library files are used and a simple "#include" statement is all that is Required to access all of the functions provided. 2. Both input and output are buffered and interrupt driven for efficiency. 3. Serial ports 1 - 4 are supported on PC, AT and PS/2 compatibles.Chained interrupts used on port 3 and 4 are allowed for so as not to interfere with devices such as a mouse or printer. Transmission speeds of 110 to 115200 baud are available. 4. Detection and utilization of hardware buffered UARTs (NS16550AF etc.) found in some machines is automatic. 5. Interrupt driven hardware and XON/XOFF flow control is provided for. 6. All source code is included. RS232.C can be used with all memory models.
標(biāo)簽： functionality provide written employ
上傳時間： 2016-08-24
上傳用戶：小眼睛LSL
The Cryptography API: Next Generation(CNG) is a new and agile framework in Windows Vista, which implements an extensible provider model that allows you to load a provider by specifying the Required cryptographic algorithm rather than having to hardcode a specific provider.
標(biāo)簽： Cryptography Generation framework Windows
上傳時間： 2013-12-18
上傳用戶：semi1981
This book is for you if You re no "dummy," and you need to get quickly up to speed in intermediate to advanced C++ You ve had some experience in C++ programming, but reading intermediate and advanced C++ books is slow-going You ve had an introductory C++ course, but you ve found that you still can t follow your colleagues when they re describing their C++ designs and code You re an experienced C or Java programmer, but you don t yet have the experience to develop nuanced C++ code and designs You re a C++ expert, and you re looking for an alternative to answering the same questions from your less-experienced colleagues over and over again C++ Common Knowledge covers essential but commonly misunderstood topics in C++ programming and design while filtering out needless complexity in the discussion of each topic. What remains is a clear distillation of the essentials Required for production C++ programming, presented in the author s trademark incisive, engaging style.
標(biāo)簽： intermediate you quickly dummy
上傳時間： 2014-01-09
上傳用戶：wpwpwlxwlx
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are Required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
標(biāo)簽： bus bidirectional primarily designed
上傳時間： 2013-12-11
上傳用戶：jeffery
Recent advances in experimental methods have resulted in the generation of enormous volumes of data across the life sciences. Hence clustering and classification techniques that were once predominantly the domain of ecologists are now being used more widely. This book provides an overview of these important data analysis methods, from long-established statistical methods to more recent machine learning techniques. It aims to provide a framework that will enable the reader to recognise the assumptions and constraints that are implicit in all such techniques. Important generic issues are discussed first and then the major families of algorithms are described. Throughout the focus is on explanation and understanding and readers are directed to other resources that provide additional mathematical rigour when it is Required. Examples taken from across the whole of biology, including bioinformatics, are provided throughout the book to illustrate the key concepts and each technique’s potential.
標(biāo)簽： experimental generation advances enormous
上傳時間： 2016-10-23
上傳用戶：wkchong
Echo a received character, RX ISR used. Normal mode is LPM0. // USART1 RX interrupt triggers TX Echo. // Baud rate divider with 1048576hz = 1048576/38400 = ~27.31 (01Bh|03h) // ACLK = LFXT1 = 32768Hz, MCLK = SMCLK = default DCO = 32 x ACLK = 1048576Hz // //* An external watch crystal between XIN & XOUT is Required for ACLK
標(biāo)簽： character interrupt received triggers
上傳時間： 2016-10-31
上傳用戶：rishian
The ISD51_Demo project for the MSC1200 shows how to use the ISD51 In-System-Debugger with flash breakpoints or hardware breakpoints. By default, it is configured for flash breakpoints which allow you to set real-time breakpoints in your software. Using Flash breakpoints has also the benefit that no special handing for the shared interrupt vector is Required, since the hardware break registers of the MSC1200 are not used at all.
標(biāo)簽： In-System-Debugger ISD the project
上傳時間： 2014-11-18
上傳用戶：dongqiangqiang
A passive optical network (PON) is a point-to-multipoint, fiber to the premises network architecture in which unpowered optical splitters are used to enable a single optical fiber to serve multiple premises, typically 32-128. A PON consists of an Optical Line Termination (OLT) at the service provider s central office and a number of Optical Network Units (ONUs) near end users. A PON configuration reduces the amount of fiber and central office equipment Required compared with point to point architectures
標(biāo)簽： network point-to-multipoint architecture premises
上傳時間： 2016-12-10
上傳用戶：王慶才
DDR SDRAM控制器的VHDL源代碼，含詳細(xì)設(shè)計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the Required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
MidasLink software including USB driver, J-Link.exe and DLL for ARM. (J-Link software including J-Flash software (license Required) can also be used with MidasLink). MidasLink software and documentation pack V3.78a [1918 kb]
標(biāo)簽： including software J-Link MidasLink
上傳時間： 2017-01-19
上傳用戶：yxgi5
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