特點 最高輸入頻率 10KHz 計數速度 50/10000脈波/秒可選擇 四種輸入模式可選擇(加算,減算,加減算,90度相位差加減算) 90度相位差加減算具有提高解析度4倍功能 輸入脈波具有預設刻度功能 前置量設定功能(二段設定)可選擇 數位化指撥設定操作簡易 計數暫時停止功能 3組報警功能 2:主要規格 脈波輸入型式: Jump-pin selectable current sourcing(NPN) or current sinking (PNP) 脈波觸發電位: HI bias (CMOS) (VIH=7.5V, VIL=5.5V) LO bias (TTL) (VIH=3.7V, VIL=2.0V) 最高輸入頻率: <10KHz (up,down,up/down mode) <5KHz (quadrature mode) 輸出動作時間 : 0.1 to 99.9 second adjustable 輸出復歸方式: Manual(N) or automatic (R or C) can be modif 繼電器容量: AC 250V-5A, DC 30V-7A 顯示值范圍: -199999 to 999999 顯示幕: Red high efficiency LEDs high 9.2mm (.36") 參數設定方式: Touch switches 感應器電源: 12VDC +/-3%(<60mA) ( 感應器電源 ) 記憶方式: Non-volatile E2PROM memory 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc (input/output) 使用環境條件: 0-50℃(20 to 90% RH non-condensed) 存放環境條件: 0-70℃(20 to 90% RH non-condensed) CE認證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上傳時間： 2013-11-12
上傳用戶：909000580
The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
上傳時間： 2014-12-30
上傳用戶：aysyzxzm
When I started writing the first edition of RF Power Amplifiers for Wireless Communications,some time back in 1997, it seemed that I was roaming a largely uninhabitedlandscape. For reasons still not clear to me there were few, if any, otherbooks dedicated to the subject of RF power amplifiers. Right at the same time, however,hundreds of engineers were being assigned projects to design PAs for wirelesscommunications products. It was not, therefore, especially difficult to be successfulwith a book that was fortuitously at the right place and the right time.
標簽： Communications Amplifiers Wireless Edition
上傳時間： 2013-11-12
上傳用戶：YYRR
ARM核心是主控SOC中的重要部分，系統的日常應用都由ARM核心來完成，因此ARM核心的效能很大程度上跟用戶體驗有關。ARM公司一般用DMIPS/MHz來標稱ARM核心的性能。DMIPS是Dhrystone Million Instructions executed Per Second的縮寫，反映核心的整數計算能力。但Dhrystone算法代碼本身比較叫，可以完全放到Cache中執行，因此反映的只是核心能力，并不能反映緩存、內存I/O性能。
上傳時間： 2013-10-16
上傳用戶：devin_zhong
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
上傳時間： 2013-10-11
上傳用戶：yuchunhai1990
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時間： 2014-01-17
上傳用戶：Altman
This is the second half of our Transistor Circuits e-book. It contains a further 100 circuits, with many of them containing one or more Integrated Circuits (ICs).It's amazing what you can do with transistors but when Integrated Circuits came along, the whole field of electronics exploded.
上傳時間： 2013-11-08
上傳用戶：603100257
飛思卡爾智能車的舵機測試程序 #include <hidef.h> /* common defines and macros */#include <MC9S12XS128.h> /* derivative information */#pragma LINK_INFO DERIVATIVE "mc9s12xs128" void SetBusCLK_16M(void) { CLKSEL=0X00; PLLCTL_PLLON=1; //鎖相環電路允許位 SYNR=0x00 | 0x01; //SYNR=1 REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK==1)); CLKSEL_PLLSEL =1; } void PWM_01(void) { //舵機初始化 PWMCTL_CON01=1; //0和1聯合成16位PWM； PWMCAE_CAE1=0; //選擇輸出模式為左對齊輸出模式 PWMCNT01 = 0; //計數器清零； PWMPOL_PPOL1=1; //先輸出高電平，計數到DTY時，反轉電平 PWMPRCLK = 0X40; //clockA 不分頻,clockA=busclock=16MHz;CLK B 16分頻:1Mhz PWMSCLA = 0x08; //對clock SA 16分頻,pwm clock=clockA/16=1MHz; PWMCLK_PCLK1 = 1; //選擇clock SA做時鐘源 PWMPER01 = 20000; //周期20ms； 50Hz; PWMDTY01 = 1500; //高電平時間為1.5ms; PWME_PWME1 = 1;
上傳時間： 2013-11-04
上傳用戶：狗日的日子
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
The Circuit Designer’s Companion Second edition Tim Williams
標簽： Designers Companion Circuit PCB
上傳時間： 2013-10-08
上傳用戶：sxdtlqqjl
