The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of SERIAL and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時間： 2014-01-17
上傳用戶：Altman
MAXQUSBJTAGOW評估板軟件:關鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique SERIAL ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標簽： MAXQUSBJTAGOW 評估板 軟件
上傳時間： 2013-10-24
上傳用戶：teddysha
用途：測量地磁方向，測量物體靜止時候的方向，測量傳感器周圍磁力線的方向。注意，測量地磁時候容易受到周圍磁場影響，主芯片HMC5883 三軸磁阻傳感器特點（抄自網上）： 1，數字量輸出：I2C 數字量輸出接口，設計使用非常方便。 2，尺寸小: 3x3x0.9mm LCC 封裝，適合大規模量產使用。 3，精度高：1－2 度，內置12 位A/D,OFFSET, SET/RESET 電路，不會出現磁飽和現象，不會有累加誤差。 4，支持自動校準程序，簡化使用步驟，終端產品使用非常方便。 5，內置自測試電路，方便量產測試，無需增加額外昂貴的測試設備。 6，功耗低：供電電壓1.8V, 功耗睡眠模式-2.5uA 測量模式-0.6mA 連接方法： 只要連接VCC，GND，SDA，SDL 四條線。 Arduino GND -> HMC5883L GND Arduino 3.3V -> HMC5883L VCC Arduino A4 (SDA) -> HMC5883L SDA Arduino A5 (SCL) -> HMC5883L SCL (注意，接線是A4，A5，不是D4,D5) 源程序： #include <Wire.h> #include <HMC5883L.h> HMC5883Lcompass; voidsetup() { SERIAL.begin(9600); Wire.begin(); compass = HMC5883L(); compass.SetScale(1.3); compass.SetMeasurementMode(Measurement_Continuous); } voidloop() { MagnetometerRaw raw = compass.ReadRawAxis(); MagnetometerScaled scaled = compass.ReadScaledAxis(); float xHeading = atan2(scaled.YAxis, scaled.XAxis); float yHeading = atan2(scaled.ZAxis, scaled.XAxis); float zHeading = atan2(scaled.ZAxis, scaled.YAxis); if(xHeading < 0) xHeading += 2*PI; if(xHeading > 2*PI) xHeading -= 2*PI; if(yHeading < 0) yHeading += 2*PI; if(yHeading > 2*PI) yHeading -= 2*PI; if(zHeading < 0) zHeading += 2*PI; if(zHeading > 2*PI) zHeading -= 2*PI; float xDegrees = xHeading * 180/M_PI; float yDegrees = yHeading * 180/M_PI; float zDegrees = zHeading * 180/M_PI; SERIAL.print(xDegrees); SERIAL.print(","); SERIAL.print(yDegrees); SERIAL.print(","); SERIAL.print(zDegrees); SERIAL.println(";"); delay(100); }
上傳時間： 2013-12-16
上傳用戶：stella2015
超聲波傳感器適用于對大幅的平面進行靜止測距。普通的超聲波傳感器測距范圍大概是 2cm~450cm，分辨率3mm（淘寶賣家說的，筆者測試環境沒那么好，個人實測比較穩定的 距離10cm~2m 左右，超過此距離就經常有偶然不準確的情況發生了，當然不排除筆者技術 問題。） 測試對象是淘寶上面最便宜的SRF-04 超聲波傳感器，有四個腳：5v 電源腳（Vcc），觸發控制端（Trig），接收端（Echo），地端（GND） 附:SRF 系列超聲波傳感器參數比較 模塊工作原理： 采用IO 觸發測距，給至少10us 的高電平信號； 模塊自動發送8個40KHz 的方波，自動檢測是否有信號返回； 有信號返回，通過IO 輸出一高電平，高電平持續的時間就是超聲波從發射到返回的時間．測試距離=(高電平時間*聲速(340m/s))/2; 電路連接方法 Arduino 程序例子： constintTrigPin = 2; constintEchoPin = 3; floatcm; voidsetup() { SERIAL.begin(9600); pinMode(TrigPin, OUTPUT); pinMode(EchoPin, INPUT); } voidloop() { digitalWrite(TrigPin, LOW); //低高低電平發一個短時間脈沖去TrigPin delayMicroseconds(2); digitalWrite(TrigPin, HIGH); delayMicroseconds(10); digitalWrite(TrigPin, LOW); cm = pulseIn(EchoPin, HIGH) / 58.0; //將回波時間換算成cm cm = (int(cm * 100.0)) / 100.0; //保留兩位小數 SERIAL.print(cm); SERIAL.print("cm"); SERIAL.println(); delay(1000); }
上傳時間： 2013-10-18
上傳用戶：星仔
虛擬串口軟件
標簽： Virtual SERIAL Driver Port
上傳時間： 2013-10-27
上傳用戶：1234321@q
MAXQUSBJTAGOW評估板軟件:關鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique SERIAL ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標簽： MAXQUSBJTAGOW 評估板 軟件
上傳時間： 2013-11-23
上傳用戶：truth12
虛擬串口軟件
標簽： Virtual SERIAL Driver Port
上傳時間： 2013-10-23
上傳用戶：JIUSHICHEN
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit SERIAL transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
3 FPGA設計流程 完整的FPGA 設計流程包括邏輯電路設計輸入、功能仿真、綜合及時序分析、實現、加載配置、調試。FPGA 配置就是將特定的應用程序設計按FPGA設計流程轉化為數據位流加載到FPGA 的內部存儲器中，實現特定邏輯功能的過程。由于FPGA 電路的內部存儲器都是基于RAM 工藝的，所以當FPGA電路電源掉電后，內部存儲器中已加載的位流數據將隨之丟失。所以，通常將設計完成的FPGA 位流數據存于外部存儲器中，每次上電自動進行FPGA電路配置加載。 4 FPGA配置原理 以Xilinx公司的Qpro Virtex Hi-Rel系列XQV100電路為例，FPGA的配置模式有四種方案可選擇：MasterSERIAL Mode，Slave SERIAL Mode，Master selectMAPMode，Slave selectMAP Mode。配置是通過芯片上的一組專/ 復用引腳信號完成的，主要配置功能信號如下： (1)M0、M1、M2：下載配置模式選擇; (2)CLK：配置時鐘信號; (3)DONE：顯示配置狀態、控制器件啟動;
上傳時間： 2013-11-18
上傳用戶：oojj
This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For information on using SERIAL Vector Format (SVF) and Xilinx SERIAL Vector Format(XSVF) files in embedded programming applications
上傳時間： 2015-01-02
上傳用戶：時代將軍
