DIY STREAM Deck，帶有LCD按鈕的開源宏鍵盤源碼DIY STREAM Deck，帶有LCD按鈕的開源宏鍵盤源碼
上傳時間： 2021-12-17
上傳用戶：XuVshu
數(shù)字圖像通信的最廣泛的應用就是數(shù)字電視廣播系統(tǒng)，與以往的模擬電視業(yè)務相比，數(shù)字電視在節(jié)省頻譜資源、提高節(jié)目質(zhì)量方面帶來了一場新的革命，而與此對應的DVB（Digital Video Broadcasting）標準的建立更是加速了數(shù)字電視廣播系統(tǒng)的大規(guī)模應用。DVB標準選定MPEG—2標準作為音頻及視頻的編碼壓縮方式，隨后對MPEG—2碼流進行打包形成TS流（transport STREAM），進行多個傳輸流復用，最后通過不同媒介進行傳輸。在DVB標準的傳輸系統(tǒng)中，無論是衛(wèi)星傳輸，電纜傳輸還是地面?zhèn)鬏敚瑸榱吮Ｕ蠄D像質(zhì)量，使數(shù)字節(jié)目在傳輸過程中避免出現(xiàn)因受到各種信道噪聲干擾而出現(xiàn)失真的現(xiàn)象，都采用了信道編碼的方式來保護傳輸數(shù)據(jù)。信道編碼是數(shù)字通信系統(tǒng)中一個必需的、重要的環(huán)節(jié)。 信道編碼設計方案的優(yōu)劣決定了DVB系統(tǒng)的成功與否，本文重點研究了DVB系統(tǒng)中的信道編碼算法及其FPGA實現(xiàn)方案，主要進行了如下幾項工作： 1）介紹了DVB系統(tǒng)信道編碼的基本概念及特點，深入研究了DVB標準中信道編碼部分的關鍵技術，并針對每個信道編碼模塊進行工作原理分析、算法分析。 2）根據(jù)DVB信道編碼的特點，重點對信道編碼中四個模塊，包括擾碼、RS編碼、卷積交織編碼和卷積編碼的FPGA硬件實現(xiàn)算法進行了比較詳細的分析，并闡述了每個模塊及QPSK調(diào)制的設計方案及實現(xiàn)模塊功能的程序流程。 3）在RS（204，188）編碼過程中，利用有限域常數(shù)乘法器的特點，對編碼器進行了優(yōu)化，在很大程度上提高了編碼效率，卷積交織器部分采用RAM移位法，實現(xiàn)起來更為簡單且節(jié)省了FPGA器件內(nèi)部資源。 4）設計以Altera公司的QuartusⅡ為開發(fā)平臺，利用FPGA芯片EP1C6Q240C8完成了信道編碼各模塊及QPSK調(diào)制的硬件實現(xiàn)，通過Verilog HDL描述和時序仿真來驗證算法的可行性，并給出系統(tǒng)設計中減少毛刺的方法，使系統(tǒng)更為穩(wěn)定。最終的系統(tǒng)仿真結果表明該系統(tǒng)工作穩(wěn)定，達到了DVB系統(tǒng)信道編碼設計的要求。
上傳時間： 2013-06-26
上傳用戶：allen-zhao123
摘要 本研究計劃之目的，在整合應用以ARM為基礎的嵌入式多媒體實時操作系統(tǒng)于H.264/MPEG-4多媒體上。由于H.264是一種因應實時系統(tǒng)(RTOS)所設計的可擴展性串流傳輸(scalability STREAM media communication)的編碼技術。H.264主要架構于細細粒可擴展(Fine Granula Scalability,FGS)的壓縮編碼機制。細粒度可擴展壓縮編碼技術是最新MPEG-4串流式傳輸標準，能依頻寛的差異來調(diào)整傳輸?shù)姆绞健＜毩６葦U展縮編碼技術以編入可選擇性的增強層(enhanced layers)于碼中，來提高影像傳輸?shù)馁|(zhì)量。本計劃主要在于設計一種簡單有效的實時階層可擴展的影像傳輸系統(tǒng)。在增強層編碼及H.264的基本層(base layer)編碼上使用漸進的細粒度可擴展編碼(Progressive Fine Granularity Scalable,PFGS)能直接使用H.264的格式特色來實現(xiàn)FGS。同時加入了LB-LLF(Layer-Based Least-Laxity-Fir stscheduling algorithm)的排程算法，來增 進網(wǎng)路傳輸影像的質(zhì)量。由實驗結果顯示本系統(tǒng)在串流影像質(zhì)量PSNR值上確有較佳的效能。
標簽： 芯片系統(tǒng) 架構 開發(fā)平臺
上傳時間： 2014-12-26
上傳用戶：mpquest
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 STREAMs (five transmit video STREAMs and five receive video STREAMs), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video STREAMs to a single output video STREAM. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video STREAMs moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-14
上傳用戶：fdmpy
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-STREAM, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
標簽： FPGA PLD 數(shù)據(jù)加密
上傳時間： 2013-11-06
上傳用戶：wl9454
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 STREAMs (five transmit video STREAMs and five receive video STREAMs), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video STREAMs to a single output video STREAM. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video STREAMs moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
上傳時間： 2013-11-23
上傳用戶：shen_dafa
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-STREAM, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
標簽： FPGA PLD 數(shù)據(jù)加密
上傳時間： 2013-10-20
上傳用戶：磊子226
A language monitor provides a full duplex communications path between the print spooler and bi-directional printers that are capable of providing software-accessible status information and adds printer control information, such as commands defined by a printer job language, to the data STREAM s.
標簽： communications language bi-direc provides
上傳時間： 2015-03-29
上傳用戶：comua
DVBSTREAM is based on the ts-rtp package available at http://www.linuxtv.org. It broadcasts a (subset of a) DVB transport STREAM over a LAN using the rtp protocol. There were a couple of small bugs in the original ts-rtp application, which I have fixed here.
標簽： broadcasts DVBSTREAM available linuxtv
上傳時間： 2013-11-30
上傳用戶：sy_jiadeyi
Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline architecture to compress and decompress images. The real filter calculation over 4 · 4 window blocks is done using a tree of carry save adders to ensure the high speed processing required for many applications. The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis reveals that the proposed architecture, implemented using current VLSI technologies, can process a video STREAM in real time.
標簽： applications processing Wavelets widely
上傳時間： 2014-01-22
上傳用戶：hongmo
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