This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 STREAMs (five transmit video STREAMs and five receive video STREAMs), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video STREAMs to a single output video
STREAM. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video STREAMs
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-STREAM, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 STREAMs (five transmit video STREAMs and five receive video STREAMs), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video STREAMs to a single output video
STREAM. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video STREAMs
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-STREAM, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
A language monitor provides a full duplex communications path between the print spooler and bi-directional printers that are capable of providing software-accessible status information and adds printer control information, such as commands defined by a printer job language, to the data STREAM s.
DVBSTREAM is based on the ts-rtp package available at
http://www.linuxtv.org. It broadcasts a (subset of a) DVB transport
STREAM over a LAN using the rtp protocol. There were a couple of
small bugs in the original ts-rtp application, which I have fixed
here.
Wavelets have widely been used in many signal and image processing applications. In this paper, a new
serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet
transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline
architecture to compress and decompress images. The real filter calculation over 4 · 4 window blocks is
done using a tree of carry save adders to ensure the high speed processing required for many applications.
The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis
reveals that the proposed architecture, implemented using current VLSI technologies, can process a
video STREAM in real time.
