單片機(jī)系統(tǒng)“PC”失控的軟件措施Software Measure of GettingO uto fC ontrolfo r“PC"in S ingleC hipC omputerS ystem謐 加 春 王 曉 基 雷 小 華(江 西 理 工 大 學(xué)機(jī) 電 工 程 學(xué) 院 ，贛 州 34 10 00)摘要單片機(jī)系統(tǒng)在實(shí)際工業(yè)現(xiàn)場(chǎng)中可能遇到各種干擾和自身的隨機(jī)性故障。現(xiàn)場(chǎng)惡劣的環(huán)境有可能使計(jì)算機(jī)系統(tǒng)發(fā)生異常，計(jì)算機(jī)程序指針“PC”失控就是常見(jiàn)的故障之一，如果發(fā)生“PC”失控，將導(dǎo)致CPI工作混亂，釀成嚴(yán)重的事故。研究了“PC”失控的原因，并指出軟件抗干擾的幾種方法，有效保證單片機(jī)系統(tǒng)的正常工作。關(guān)鍵詞單片機(jī)“PC”失控抗干擾Abstract Inp racticalin dustrialfi elds,th ereis v ariousin terferencea fectingo perationo fsi nglec hipc omputersy stemsa ndt hec omputersy stems。fac噸random faults飾themselves. It is very common that the severe environment makes the computer SYSTEMS abnormal. The program counter "PC"gettingo utof co ntorlis on eo fth ec ommonfa ults.If th isoc curs,C PUw ouldb eru nningo utof or deran din torducesse riousan cient.T hec ausesof " PC"geting out of control， studied in this paper and some countermeasures of anti-interference師software are given to ensure single chip computer systemworking properly.Keywords Single。飾computer Porgramc ounter"P C" Anti-interfeernc 在設(shè) 計(jì) 和 開(kāi)發(fā)單片機(jī)系統(tǒng)時(shí)，一般難以周全地預(yù)計(jì)單片機(jī)系統(tǒng)在實(shí)際工業(yè)現(xiàn)場(chǎng)中可能遇到的各種干擾和自身的隨機(jī)性故障。因此，除了采取防止和抑制干擾的各項(xiàng)措施外，還應(yīng)該借助于軟件措施克服某些干擾，系統(tǒng)還應(yīng)具備迅速自行恢復(fù)的能力。本文介紹的應(yīng)對(duì)單片機(jī)系統(tǒng)PC失控的軟件措施，設(shè)計(jì)靈活，節(jié)省硬件資源，能保證測(cè)控系統(tǒng)長(zhǎng)期可靠地運(yùn)行。MC S- 5 1單片機(jī)以其優(yōu)良的性能價(jià)格比大量應(yīng)用于工業(yè)現(xiàn)場(chǎng)測(cè)試和控制領(lǐng)域。但是，現(xiàn)場(chǎng)惡劣的環(huán)境有可能使計(jì)算機(jī)系統(tǒng)發(fā)生異常，計(jì)算機(jī)程序指針PC失控就是常見(jiàn)的故障之一，一旦發(fā)生PC“走飛”，計(jì)算機(jī)系統(tǒng)就會(huì)出現(xiàn)工作混亂，釀成嚴(yán)重的事故。為 了 在 CP 失控時(shí)盡量減少由此帶來(lái)的不利影響，并盡快使系統(tǒng)恢復(fù)正常，需要采取一定的軟件措施和硬件措施。常見(jiàn)的硬件措施有“看門(mén)狗”電路。軟件措施設(shè)置的前提條件是:①在干擾作用下，微機(jī)系統(tǒng)硬件部分不會(huì)受到任何損壞，或者損壞部分設(shè)置有監(jiān)測(cè)狀態(tài)可供查詢;②程序區(qū)不會(huì)受到干擾侵害。單片機(jī)系統(tǒng)的程序和表格以及重要的參數(shù)均設(shè)置在ROM區(qū)，不會(huì)因干擾的侵人而改變;③ RAM區(qū)中的重要數(shù)據(jù)不會(huì)被破壞，或者雖然被破壞，但是可以重新建立。
標(biāo)簽： 單片機(jī)系統(tǒng) 軟件
上傳時(shí)間： 2013-11-02
上傳用戶：bhqrd30
The PL2303 USB to Serial adapter is your smart and convenient accessory forconnecting RS-232 serial devices to your USB-equipped Windows host computer. Itprovides a bridge connection with a standard DB 9-pin male serial port connector inone end and a standard Type-A USB plug connector on the other end. You simplyattach the serial device onto the serial port of the cable and plug the USB connectorinto your PC USB port. It allows a simple and easy way of adding serial connectionsto your PC without having to go thru inserting a serial card and traditional portconfiguration.This USB to Serial adapter is ideal for connecting modems, cellular phones, PDAs,digital cameras, card readers and other serial devices to your computer. It providesserial connections up to 1Mbps of data transfer rate. And since USB does not requireany IRQ resource, more devices can be attached to the system without the previoushassles of device and resource conflicts.Finally, the PL-2303 USB to Serial adapter is a fully USB Specification compliantdevice and therefore supports advanced power management such as suspend andresume operations as well as remote wakeup. The PL-2303 USB Serial cable adapteris designed to work on all Windows operating SYSTEMS.
標(biāo)簽： Adapter Serial 2303 USB
上傳時(shí)間： 2013-11-01
上傳用戶：ghostparker
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in SYSTEMS with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in SYSTEMS requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
There has long been a need for portable ultrasoundSYSTEMS that have good resolution at affordable costpoints. Portable SYSTEMS enable healthcare providersto use ultrasound in remote locations such asdisaster zones, developing regions, and battlefields,where it was not previously practical to do so.
標(biāo)簽： Xilinx 便攜式 超聲系統(tǒng) 器件
上傳時(shí)間： 2013-10-26
上傳用戶：liulinshan2010
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety SYSTEMS in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety SYSTEMS is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety SYSTEMS include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control SYSTEMS in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related SYSTEMS,” is understood as the standard for designing safety SYSTEMS for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety SYSTEMS in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
標(biāo)簽： FPGA 安全系統(tǒng)
上傳時(shí)間： 2013-11-05
上傳用戶：維子哥哥
Design techniques for electronic SYSTEMS areconstantly changing. In industries at the heart of thedigital revolution, this change is especially acute.Functional integration, dramatic increases incomplexity, new standards and protocols, costconstraints, and increased time-to-market pressureshave bolstered both the design challenges and theopportunities to develop modern electronic SYSTEMS.One trend driving these changes is the increasedintegration of core logic with previously discretefunctions to achieve higher performance and morecompact board designs.
標(biāo)簽： System Xilinx FPGA 151
上傳時(shí)間： 2014-12-28
上傳用戶：康郎
The standard that governs the design of avioniccomponents and SYSTEMS, DO-254, is one of the mostpoorly understood but widely applicable standardsin the avionic industry. While information on thegeneral aspects of the standard is easy to obtain, thedetails of exactly how to implement the standard aresketchy. And once an entity develops a process thatachieves compliance, the details of how compliancewas achieved become part of the intellectualproperty of that entity. This white paper focuses onthe details of developing a DO-254 compliantprocess for the design of FPGAs.
上傳時(shí)間： 2013-11-12
上傳用戶：q123321
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded SYSTEMS, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
標(biāo)簽： xilinx Zynq 7000 EPP
上傳時(shí)間： 2013-11-01
上傳用戶：dingdingcandy
XAPP520將符合2.5V和3.3V I/O標(biāo)準(zhǔn)的7系列FPGA高性能I/O Bank進(jìn)行連接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V SYSTEMS
上傳時(shí)間： 2013-11-19
上傳用戶：yyyyyyyyyy
針對(duì)嵌入式機(jī)器視覺(jué)系統(tǒng)向獨(dú)立化、智能化發(fā)展的要求，介紹了一種嵌入式視覺(jué)系統(tǒng)--智能相機(jī)。基于對(duì)智能相機(jī)體系結(jié)構(gòu)、組成模塊和圖像采集、傳輸和處理技術(shù)的分析，對(duì)國(guó)內(nèi)外的幾款智能相機(jī)進(jìn)行比較。綜合技術(shù)發(fā)展現(xiàn)狀，提出基于FPGA+DSP模式的硬件平臺(tái)，并提出智能相機(jī)的發(fā)展方向。分析結(jié)果表明，該系統(tǒng)設(shè)計(jì)可以實(shí)現(xiàn)脫離PC運(yùn)行，完成圖像獲取與分析，并作出相應(yīng)輸出。 Abstract: This paper introduced an embedded vision system-intelligent camera ，which was for embedded machine vision SYSTEMS to an independent and intelligent development requirements. Intelligent camera architecture， component modules and image acquisition， transmission and processing technology were analyzed. After comparing integrated technology development of several intelligent cameras at home and abroad， the paper proposed the hardware platform based on FPGA+DSP models and made clear direction of development of intelligent cameras. On the analysis of the design， the results indicate that the system can run from the PC independently to complete the image acquisition and analysis and give a corresponding output.
標(biāo)簽： FPGA DSP 模式 智能相機(jī)
上傳時(shí)間： 2013-10-24
上傳用戶：bvdragon
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