This tutorial explains how the SDRAM chip on ltera’s DE2 Development and Education board can be used with a Nios II system implemented by using the Altera SOPC Builder.
HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline.
HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim.
HSSDRC IP core is licensed under MIT License
