提出了一個(gè)由AT89C52單片機(jī)控制步進(jìn)電機(jī)的實(shí)例。可以通過(guò)鍵盤輸入相關(guān)數(shù)據(jù), 并根據(jù)需要, 實(shí)時(shí)對(duì)步進(jìn)電機(jī)工作方式進(jìn)行設(shè)置, 具有實(shí)時(shí)性和交互性的特點(diǎn)。該系統(tǒng)可應(yīng)用于步進(jìn)電機(jī)控制的大多數(shù)場(chǎng)合。實(shí)踐表明, 系統(tǒng)性能優(yōu)于傳統(tǒng)的步進(jìn)電機(jī)控制器。關(guān)鍵詞: 單片機(jī); 步進(jìn)電動(dòng)機(jī); 直流固態(tài)繼電器; 實(shí)時(shí)控制Con trol System of Stepp ingMotor Ba sed on AT89C52 ChipM icrocomputerMENGWu2sheng, L ILiang (College of Automatization, Northwestern Polytechnical Unversity, Xipan 710072, China)ABSTRACT: A stepp ing motor control system based on AT89C52 chip microcomputer was described.The data can be inputwith keyboard, and stepp ingmotorwas controlled by these data. According to the demand, users can Set the workingmodel of stepp ingmotor in real2time. This system can be widely used in stepp ing motor controlling. The p ractice showed that the performance of this system outdid the tradi tional stepp ing motor controller.KEY WORDS: Chip microcomputer; Stepp ingmotor; DCSSR; Real2time control
標(biāo)簽： Control System ingMot Stepp
上傳時(shí)間： 2013-11-19
上傳用戶：leesuper
MCSÉ-51 Programmer's Guide and Instruction Set The information presented in this chapter is collected from the MCSÉ-51 Architectural Overview and the HardwareDescription of the 8051, 8052 and 80C51 chapters of this book. The material has been selected and rearranged toform a quick and convenient reference for the programmers of the MCS-51. This guide pertains specifically to the8051, 8052 and 80C51.
標(biāo)簽： Program Eacute MCS 51
上傳時(shí)間： 2013-11-13
上傳用戶：hj_18
The AT89C52 is a low-power, high-performance CMOS 8-bit microcomputer with 8Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atmel’s high-density nonvolatile memory technology and iscompatible with the industry-standard 80C51 and 80C52 instruction Set and pinout.The on-chip Flash allows the program memory to be reprogrammed in-system or by aconventional nonvolatile memory programmer. By combining a versatile 8-bit CPUwith Flash on a monolithic chip, the Atmel AT89C52 is a powerful microcomputerwhich provides a highly-flexible and cost-effective solution to many embedded controlapplications.
上傳時(shí)間： 2013-11-10
上傳用戶：1427796291
什么是JTAG 到底什么是JTAG呢？ JTAG(Joint Test Action Group)聯(lián)合測(cè)試行動(dòng)小組)是一種國(guó)際標(biāo)準(zhǔn)測(cè)試協(xié)議（IEEE 1149.1兼容），主要用于芯片內(nèi)部測(cè)試。現(xiàn)在多數(shù)的高級(jí)器件都支持JTAG協(xié)議，如DSP、FPGA器件等。標(biāo)準(zhǔn)的JTAG接口是4線：TMS、 TCK、TDI、TDO，分別為模式選擇、時(shí)鐘、數(shù)據(jù)輸入和數(shù)據(jù)輸出線。 JTAG最初是用來(lái)對(duì)芯片進(jìn)行測(cè)試的，基本原理是在器件內(nèi)部定義一個(gè)TAP（Test Access Port�測(cè)試訪問(wèn)口）通過(guò)專用的JTAG測(cè)試工具對(duì)進(jìn)行內(nèi)部節(jié)點(diǎn)進(jìn)行測(cè)試。JTAG測(cè)試允許多個(gè)器件通過(guò)JTAG接口串聯(lián)在一起，形成一個(gè)JTAG鏈，能實(shí)現(xiàn)對(duì)各個(gè)器件分別測(cè)試。現(xiàn)在，JTAG接口還常用于實(shí)現(xiàn)ISP（In-System rogrammable�在線編程），對(duì)FLASH等器件進(jìn)行編程。 JTAG編程方式是在線編程，傳統(tǒng)生產(chǎn)流程中先對(duì)芯片進(jìn)行預(yù)編程現(xiàn)再裝到板上因此而改變，簡(jiǎn)化的流程為先固定器件到電路板上，再用JTAG編程，從而大大加快工程進(jìn)度。JTAG接口可對(duì)PSD芯片內(nèi)部的所有部件進(jìn)行編程 JTAG的一些說(shuō)明 通常所說(shuō)的JTAG大致分兩類，一類用于測(cè)試芯片的電氣特性，檢測(cè)芯片是否有問(wèn)題；一類用于Debug；一般支持JTAG的CPU內(nèi)都包含了這兩個(gè)模塊。 一個(gè)含有JTAG Debug接口模塊的CPU，只要時(shí)鐘正常，就可以通過(guò)JTAG接口訪問(wèn)CPU的內(nèi)部寄存器和掛在CPU總線上的設(shè)備，如FLASH，RAM，SOC（比如4510B，44Box，AT91M系列）內(nèi)置模塊的寄存器，象UART，Timers，GPIO等等的寄存器。 上面說(shuō)的只是JTAG接口所具備的能力，要使用這些功能，還需要軟件的配合，具體實(shí)現(xiàn)的功能則由具體的軟件決定。 例如下載程序到RAM功能。了解SOC的都知道，要使用外接的RAM，需要參照SOC DataSheet的寄存器說(shuō)明，設(shè)置RAM的基地址，總線寬度，訪問(wèn)速度等等。有的SOC則還需要Remap，才能正常工作。運(yùn)行Firmware時(shí)，這些設(shè)置由Firmware的初始化程序完成。但如果使用JTAG接口，相關(guān)的寄存器可能還處在上電值，甚至?xí)r錯(cuò)誤值，RAM不能正常工作，所以下載必然要失敗。要正常使用，先要想辦法設(shè)置RAM。在ADW中，可以在Console窗口通過(guò)Let 命令設(shè)置，在AXD中可以在Console窗口通過(guò)Set命令設(shè)置。
上傳時(shí)間： 2013-10-23
上傳用戶：aeiouetla
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to Set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-14
上傳用戶：fdmpy
There is no doubt that remote controls are extremely popular and it has become very hard to imagine a world without them. They are used to control all manner of house appliances like the TV Set, the stereo, the VCR, and the satellite receiver.
上傳時(shí)間： 2013-11-13
上傳用戶：頂?shù)弥?/p>
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note describes how to Set up thespecific clocking structure required for the SerDes interface and the constraints to be added tothe UCF file. This reference system is complete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.
上傳時(shí)間： 2013-11-01
上傳用戶：truth12
本文主要通過(guò)介紹PLC通訊的意義和三菱FX系列PLC的四種通訊方式，并重點(diǎn)介紹FX系列PLC與計(jì)算機(jī)無(wú)協(xié)議通訊，主要從無(wú)協(xié)議通訊的硬件、配線、數(shù)據(jù)寄存器設(shè)置、PLC與計(jì)算機(jī)無(wú)協(xié)議通訊的指令用法、PLC程序編寫和計(jì)算機(jī)VB程序的編寫來(lái)說(shuō)明無(wú)協(xié)議通訊的過(guò)程和一般方法。 My dissertation introduces the significance of PLC communications and the four means of communication of Mitsubishi FX’s PLC, And highlights the no protocol communications of FX series PLC and computer, no protocol communications hardware, wiring, Register data Set, and the usage of command about no protocol communications, How to write PLC program and computer VB program to illustrate the process of no protocol communications and general method.
標(biāo)簽： PLC 三菱FX系列 計(jì)算機(jī) 協(xié)議
上傳時(shí)間： 2014-11-29
上傳用戶：Jerry_Chow
This application note provides step-by-step instructions on how to recreate a Tri-Mode Ethernet(TEMAC) performance testing system using the ML405 board and MontaVista Linux 4.0. Thisapplication note shows how to Set up a simple EDK Base System Builder system on the ML405Evaluation Platform and run performance tests. The network architecture for the test isdescribed. A system is built and downloaded into the FPGA. A MontaVista Linux kernel isconfigured, built, and downloaded into the ML405 Evaluation Platform. The instructions forobtaining and Setting up the software used to perform the measurements, netperf, are given.
標(biāo)簽： Virtex TEMAC XAPP 1023
上傳時(shí)間： 2013-11-11
上傳用戶：saharawalker
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction Set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上傳時(shí)間： 2013-11-07
上傳用戶：swing
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