This m file analyzes a coherent binary phase Shift keyed(BPSK) and a amplitude Shift keyed(ASK) communication system. The receiver uses a correlator(mixer-integrator[LPF]) configuration with BER measurements comparing measured and theoretical results. The bandpass and low pass used in the receiver are constructed using z transforms.
VHDL實現(xiàn)SPI功能源代碼
-- The SPI bus is a 3 wire bus that in effect links a serial Shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit Shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave Shift their Shift registers 8 bits and thus exchange their 8
-- bit register values.
