-- DESCRIPTION : Shift register -- Type : univ -- Width : 4 -- Shift direction: right/left (right active high) -- -- CLK active : high -- CLR active : high -- CLR type : synchronous -- SET active : high -- SET type : synchronous -- LOAD active : high -- CE active : high -- SERIAL input : SI
標簽： Shift right DESCRIPTION direction
上傳時間： 2013-12-02
上傳用戶：gxrui1991
Images with Uncertainty Efficient Algorithms for Shift, Rotation, Scaling, and Registration, and Their Applications to Geosciences (2007).pdf
標簽： Registration Uncertainty Algorithms Efficient
上傳時間： 2016-08-23
上傳用戶：zhaiye
MSP-FET430P140 Demo - USART0, SPI Interface to HC165/164 Shift Registers Description: Demonstrate USART0 in two-way SPI mode. Data are read from an HC165, and same data written back to the HC164. ACLK = n/a MCLK = SMCLK = default DCO = UCLK0 = DCO/2 * USART0 control bits are in different SFR s from other MSP430 s *
標簽： Description Demonstrate Interface Registers
上傳時間： 2013-12-28
上傳用戶：懶龍1988
按五次Shift鍵,就會出現一個功能界面通過它你可以調用網頁
上傳時間： 2013-12-21
上傳用戶：ggwz258
使用89S52為核心做的USB鍵盤,注意修改了一下windows設備描述符以及端點處理等就行了。用了一個4*4的小鍵盤,有0-9十個數字鍵, Num Lock鍵,Caps Lock鍵,Shift鍵,Ctrl鍵,Alt鍵,回車鍵等。 最多可以有三個鍵同時按下，如果相交的話，最多只能兩個鍵按下
上傳時間： 2013-12-14
上傳用戶：zhuimenghuadie
簡易MIPS CPU程式碼 此CPU包含 Shift add sub and or stl beq lw sw 等功能
上傳時間： 2014-01-18
上傳用戶：CHENKAI
雙系統用戶 粘滯鍵漏洞 Shift按五下輕松破解Vista登陸密碼
上傳時間： 2016-10-31
上傳用戶：xwd2010
Top module name : ShiftER (File name : ShiftER.v) 2. Input pins: Shift [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The Shift signal describes the Shift number. The Shift range is 0 to 15. 6. When the signal RIGHT is high, it Shifts input data to right. On the other hand, it Shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it Shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上傳時間： 2013-12-13
上傳用戶：himbly
Top module name : ShiftER (File name : ShiftER.v) 2. Input pins: Shift [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The Shift signal describes the Shift number. The Shift range is 0 to 15. 6. When the signal RIGHT is high, it Shifts input data to right. On the other hand, it Shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it Shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上傳時間： 2014-01-20
上傳用戶：三人用菜
This m file simulates a differential phase Shift keyed (DPSK) ultra wide bandwidth(UWB) system using a fifth derivative waveform equation of a Gaussian pulse.
標簽： differential bandwidth simulates system
上傳時間： 2014-01-03
上傳用戶：784533221
