對于瀝青混凝土攤鋪機自動找平控制系統來說，數字式控制系統的研制是目前的一個方向。介紹了一種基于CAN總線的數字式自動找平控制系統。該系統以CAN總線作為通信方式，PWM控制信號通過C8051F040單片機內部PCA可編程計數器陣列產生，并具有結構簡單、信號穩定、實時性強、易擴展的特點。通過硬件實現和系統運行達到了比較理想的控制效果，驗證了系統的可行性。 Abstract: A digital auto-leveling control system based on CAN Bus is introduced.It uses CAN Bus as the method of communication and creates PWM Signals by programmable counter array in C8051F040 microcontroller. The system is simple, stable, real-time and expansive.
上傳時間： 2013-10-09
上傳用戶：ligi201200
介紹了CAN總線和P87C591單片機的特點，給出了基于P87C591單片機的信號采集節點的軟、硬件設計，指出了硬件電路設計中應注意的問題，在軟件設計中重點介紹了節點初始化、報文發送和報文接收等子程序。 Abstract: The features of CAN Bus and the microcontroller P87C591 are introduced, and the design of hardware circuit and soft configuration of the Signals collection node based on P87C591 are presented. The problems in designing hardware circuit are discussed.Initialization subprogram, transmiting subprogram and receiving subprogram are emphasized in soft configuration.
上傳時間： 2013-11-03
上傳用戶：BIBI
為解決傳統可視倒車雷達視頻字符疊加器結構復雜，可靠性差，成本高昂等問題，在可視倒車雷達設計中采用視頻字符發生器芯片MAX7456。該芯片集成了所有用于產生用戶定義OSD，并將其插入視頻信號中所需的全部功能，僅需少量的外圍阻容元件即可正常工作。給出了以MAX7456為核心的可視倒車雷達的軟、硬件實現方案及設計實例。該方案具有電路結構簡單、價格低廉、符合人體視覺習慣的特點。經實際裝車測試，按該方案設計的可視倒車雷達視場清晰、提示字符醒目、工作可靠，可有效降低駕駛員倒車時的工作強度、減少倒車事故的發生。 Abstract: A new video and text generation chip，MAX7456，was used in the design of video parking sensor in order to simplify system structure，improve reliability and reduce cost. This chip included all the necessary functions to generate user-defined OSDs and to add them into the video Signals. It could be put into work with addition of just a small number of resistances and capacitors. This paper provided software and hardware implementation solutions and design example based on the chip. The system had the characteristics of simplicity in circuit structure，lower cost，and comfort for the nature of human vision. Loading road test demonstrates high video and text display quality and reliable performance，which makes the driver easy to see backward and reduces chance of accidents.
上傳時間： 2013-12-10
上傳用戶：qiaoyue
The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus Signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAT25128 device. The device featuressoftware and hardware write protection, including partial as well as full array protection.
上傳時間： 2013-11-15
上傳用戶：fklinran
The P82B96 offers many different ways in which it can be used as abus interface. In its simplest application it can be used as aninterface between bus systems operating from different supplyvoltages. Opto isolation between two bus systems is possible, andalso the availability of the Tx and Rx Signals permits interfacing ofthe P82B96 with other bus systems which separate the forwardoutput path, from the backward input signal path.
上傳時間： 2013-10-11
上傳用戶：洛木卓
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input Signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput Signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput Signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input Signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上傳時間： 2013-10-23
上傳用戶：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input Signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput Signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput Signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上傳時間： 2014-04-02
上傳用戶：han_zh
The 87C576 includes two separate methods of programming theEPROM array, the traditional modified Quick-Pulse method, and anew On-Board Programming technique (OBP).Quick Pulse programming is a method using a number of devicepins in parallel (see Figure 1) and is the traditional way in which87C51 family members have been programmed. The Quick-Pulsemethod supports the following programming functions:– program USER EPROM– verify USER EPROM– program KEY EPROM– program security bits– verify security bits– read signature bytesThe Quick-Pulse method is quite easily suited to standardprogramming equipment as evidenced by the numerous vendors of87C51 compatible programmers on the market today. Onedisadvantage is that this method is not well suited to programming inthe embedded application because of the large number of signallines that must be isolated from the application. In addition, parallelSignals from a programmer would need to be cabled to theapplication’s circuit board, or the application circuit board wouldneed to have logic built-in to perform the programming functions.These requirements have generally made in-circuit programmingusing the modified Quick Pulse method impractical in almost all87C51 family applications.
上傳時間： 2013-10-21
上傳用戶：xiaozhiqban
在綜合分析諧波勵磁無刷同步發電機勵磁控制系統的基礎上,對其勵磁控制策略進行了研究,開發了一套基于DSP( TMS320F2812) 控制的新型柴油發電機勵磁控制系統,該系統采用參數自適應模糊PID 控制勵磁,選用交流采樣方式實時檢測各信號的瞬時特性,系統仿真結果以及在1 臺25 kW 工頻柴油發電機上的試驗結果證明了該控制器具有較好的電壓調節特性,系統穩態和暫態性能完全滿足發電機對勵磁系統的要求。關鍵詞:勵磁調節;模糊PID 控制;數字信號處理器;交流采樣 Abstract :According to the general analysis of the excitation cont rol system of the harmonious wave excitation brushless synchronous generator and it s characteristics ,a new type of diesel generator excitation cont rol system based on DSP( TMS320F2812) was designed. An adaptive fuzzy PID cont rol of excitation is used in this system. To detect the t ransient characteristics of the Signals in a timely manner ,AC sampling was applied.The system simulation result s and the testing result s f rom a 25 kW diesel generator (50 Hz) can prove that the voltage regulation characteristics of the excitation cont rol system are very well ,and both the steadyOstate performance and the t ransient performance of the generator are also good.Key words :excitation cont rol ;fuzzy PID cont rol ;digital signal processor (DSP) ;AC sampling
上傳時間： 2013-10-29
上傳用戶：fxf126@126.com
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode Signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
標簽： Spartan-XL Express XAPP FPGA
上傳時間： 2014-12-28
上傳用戶：hewenzhi
