為了能夠滿足基站易于選址、優(yōu)質(zhì)快速的建站要求和易維護、低成本、高可靠的運行要求，本文對以方艙來實現(xiàn)一體化結(jié)構(gòu)基站做出一番探討。從系統(tǒng)設(shè)計的觀點闡述了移動通信高性能基站天線設(shè)計的幾個關(guān)鍵問題，介紹了智能天線技術(shù)在基站中的應(yīng)用，并且用HFSS軟件仿真了一種新型的對稱陣子天線，該天線駐波比小于2的帶寬可以達到60%，具有良好的寬頻帶特性。 Abstract: In order to meet the station construction requirement of easy site selection and fast base station， and meet the operational requirement of easy maintenance， low cost and high reliability， this paper discussed the unified architecture base station using shelter. Several key problems of high performance mobile communication base station antenna were illustrated from the view of system design， the application of smart antenna in base station was also introduced. And a novel dipole antenna was Simulated by using HFSS， the VSWR of the antenna is less than 2， and the bandwidth was reach to 60%. So it has good broadband properties.
標簽： 智能天線 基站 中的應(yīng)用
上傳時間： 2013-11-20
上傳用戶：linlin
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對移相（QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達到了預(yù)期的設(shè)計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and Simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計
上傳時間： 2013-10-28
上傳用戶：jyycc
基于通用集成運算放大器，利用MASON公式設(shè)計了一個多功能二階通用濾波器，能同時或分別實現(xiàn)低通、高通和帶通濾波，也能設(shè)計成一個正交振蕩器。電路的極點頻率和品質(zhì)因數(shù)能夠獨立、精確地調(diào)節(jié)。電路使用4個集成運放、2個電容和11個電阻，所有集成運放的反相端虛地。利用計算機仿真電路的通用濾波功能、極點頻率和品質(zhì)因數(shù)的獨立控制和正交正弦振蕩，從而證明該濾波器正確有效。 Abstract: A new multifunctional second-order filter based on OPs was presented by MASON formula. Functions， such as high-pass， band-pass， low-pass filtering， can be realized respectively and simultaneously， and can become a quadrature oscillator by modifying resistance ratio. Its pole angular frequency and quality factor can be tuned accurately and independently. The circuit presented contains four OPs， two capacitors， and eleven resistances， and inverting input of all OPs is virtual ground. Its general filtering， the independent control of pole frequency and quality factor and quadrature sinusoidal oscillation were Simulated by computer， and the result shows that the presented circuit is valid and effective.
標簽： MASON 多功能 二階 濾波器設(shè)計
上傳時間： 2013-10-09
上傳用戶：13788529953
For the incomplete methods, we kept the representation of the queens by a table and the method of calculation to determine if two queens are in conflict, which is much faster for this kind of problems than the representation by a matrix. heuristics: descent. Tests: 100 queens in less than 1 second and 67 iterations. 500 queens in 1 second and 257 iterations. 1000 queens in 11 seconds and 492 iterations. heuristics: Simulated annealing. Tests: 100 queens in less than 1 second and 47 iterations. 500 queens in 5 seconds and 243 iterations. 1000 queens in 13 seconds and 497 iterations. heuristics: based on Simulated Annealing. Tests: 100 queens in less than 1 second and 60 iterations. 500 queens in 1 second and 224 iterations. 1000 queens in 5 seconds and 459 iterations. 10 000 queens in 20 minutes 30 seconds and 4885 iterations.
標簽： the representation incomplete methods
上傳時間： 2015-05-05
上傳用戶：1159797854
The Network Security Response Framework (NSRF) allows for testing different computer security response engines and methodologies. It supports Simulated and real: Intrusion Detection Systems (sensors), Attacks, and Responses.
標簽： Framework different Security Response
上傳時間： 2013-12-03
上傳用戶：ippler8
THIS M-FILE USES THE TRANFER MATRIX METHOD TO EVALUATE THE COUPLED-MODE ％EQUATIONS. THE REFLECTION SPECTRUM OF THE GRATING AND THE TRANSMISSION ％SPECTRUM, DELAY AND DISPERSION OF THE FABRY-PEROT FILTER ARE Simulated
標簽： THE COUPLED-MODE REFLECTION EQUATIONS
上傳時間： 2015-08-11
上傳用戶：CHINA526
藍牙跳頻系統(tǒng)的simulink仿真程序（This is a MATLAB simulation (SIMULINK) for the hop selection scheme in Bluetooth. Since nearly the same scheme is used for 79 and 23-hop system. Only the 79-hop system in Simulated in the CONNECTION state.）
標簽： simulation Bluetooth selection simulink
上傳時間： 2013-12-19
上傳用戶：wanqunsheng
A one-dimensional calibration object consists of three or more collinear points with known relative positions. It is generally believed that a camera can be calibrated only when a 1D calibration object is in planar motion or rotates around a ¯ xed point. In this paper, it is proved that when a multi-camera is observing a 1D object undergoing general rigid motions synchronously, the camera set can be linearly calibrated. A linear algorithm for the camera set calibration is proposed，and then the linear estimation is further re¯ ned using the maximum likelihood criteria. The Simulated and real image experiments show that the proposed algorithm is valid and robust.
標簽： one-dimensional calibration collinear consists
上傳時間： 2014-01-12
上傳用戶：璇珠官人
This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be Simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
標簽： Development Startix2 tailored Altera
上傳時間： 2014-01-19
上傳用戶：chongcongying
驅(qū)動級IO模擬按鍵，用于DX游戲的按鍵模擬。 this code can IO-driven simulation of the keys to the game for the DX Simulated keys.
上傳時間： 2013-12-24
上傳用戶：silenthink
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