A spatiotemporal chaotic map is digitized to develop a highly paralleled PRBS generator that accommodates to FPGA (Field Programmable Gate Array) implementation in present paper.
標簽： spatiotemporal paralleled digitized generator
上傳時間： 2013-12-12
上傳用戶：Andy123456
數字示波器功能強大,使用方便,但是價格相對昂貴。本文以Ti的MSP430F5529為主控器,以Altera公司的EP2C5T144C8 FPGA器件為邏輯控制部件設計數字示波器。模擬信號經程控放大、整形電路后形成方波信號送至FPGA測頻,根據頻率值選擇采用片上及片外高速AD分段采樣。FPGA控制片外AD采樣并將數據輸入到FIFO模塊中緩存,由單片機進行頻譜分析。測試表明:簡易示波器可以實現自動選檔、多采樣率采樣、高精度測頻及頻譜分析等功能。Digital oscilloscope is powerful and easy to use, but also expensive. The research group designed a low-cost digital oscilloscope, the chip of MSP430F5529 of TI is chosen as the main controller and the device of EP2C5T144C8 of Altera company is used as the logic control unit. Analog signal enter the programmable amplifier circuit, shaping circuit and other pre-processing circuit. The shaped rectangular wave signal is sent to FPGA for measure the frequency. According to the frequency value to select AD on-chip or off-chip high-speed AD for sampling. FPGA controls the off-chip AD sampling and buffers AD data by FIFO module. The single chip microcomputer receives the data, and do FFT for spectrum analysis. The test shows that the simple oscilloscope can realize automatic gain selection, sampling at different sampling rates, high precision frequency measurement and spectrum analysis.
上傳時間： 2022-03-27
上傳用戶：
Xilinx的FPGA 中的matlab simulink建模，內有幾種調制方式，比如QPSK等
標簽： simulink Xilinx matlab FPGA
上傳時間： 2013-08-16
上傳用戶：zhishenglu
fpga this will help you to improve you ability
上傳時間： 2013-08-19
上傳用戶：417313137
分析了MATLAB/Simulink 中DSP Builder 模塊庫在FPGA 設計中優點，\\r\\n然后結合FSK 信號的產生原理，給出了如何利用DSP Builder 模塊庫建立FSK 信號發生器模\\r\\n型，以及對FSK 信號發生器模型進行算法級仿真和生成VHDL 語言的方法，并在modelsim\\r\\n中對FSK 信號發生器進行RTL 級仿真，最后介紹了在FPGA 芯片中實現FSK 信號發生器的設\\r\\n計方法。
標簽： Simulink Builder MATLAB FPGA
上傳時間： 2013-08-20
上傳用戶：herog3
this a book about how to use fpga,it is very simply ,but is useful for developing fpga,
上傳時間： 2013-08-30
上傳用戶：debuchangshi
My thesis entitled \"fpga digital clock,\" immature, to enlighten
上傳時間： 2013-08-31
上傳用戶：smallfish
關于FPGA流水線設計的論文\r\nThis work investigates the use of very deep pipelines for\r\nimplementing circuits in FPGAs, where each pipeline\r\nstage is limited to a single FPGA logic element (LE). The\r\narchitecture and VHDL design of a parameterized integer\r\na
上傳時間： 2013-09-03
上傳用戶：wl9454
針對使用硬件描述語言進行設計存在的問題，提出一種基于FPGA并采用DSP Builder作為設計工具的數字信號處理器設計方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ設計流程，設計了一個12階FIR 低通數字濾波器，通過Quartus 時序仿真及嵌入式邏輯分析儀SignalTapⅡ硬件測試對設計進行了驗證。結果表明，所設計的FIR 濾波器功能正確，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
上傳時間： 2013-11-17
上傳用戶：lo25643
As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-sensitive markets. Application classes like
上傳時間： 2013-11-10
上傳用戶：XLHrest
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