The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency Specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency Specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時(shí)間： 2013-11-24
上傳用戶：18707733937
Xilinx is disclosing this user guide, manual, release note, and/or Specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： CPLD
上傳時(shí)間： 2014-12-05
上傳用戶：qazxsw
Silicon Motion, Inc. has made best efforts to ensure that the information contained in this document is accurate andreliable. However, the information is subject to change without notice. No responsibility is assumed by SiliconMotion, Inc. for the use of this information, nor for infringements of patents or other rights of third parties.Copyright NoticeCopyright 2002, Silicon Motion, Inc. All rights reserved. No part of this publication may be reproduced, photocopied,or transmitted in any form, without the prior written consent of Silicon Motion, Inc. Silicon Motion, Inc. reserves theright to make changes to the product Specification without reservation and without notice to our users
標(biāo)簽： GUIDELINES LAYOUT 320 PCB
上傳時(shí)間： 2013-10-10
上傳用戶：manga135
為了改進(jìn)產(chǎn)品性能和兼容性，最新的HDMI compliance test Specification (HDMI CTS) V.1.3增加了新的測(cè)試內(nèi)容和定下了更嚴(yán)格的標(biāo)準(zhǔn)。大多數(shù)現(xiàn)在遞交給HDMI授權(quán)測(cè)試中心(ATC) 的帶有HDMI功能的電器都將按照HDMI CTS V.1.3 來測(cè)試。Analog Devices (ADI) 分別在美國的綠堡(Greensboro，NC), 東京, 臺(tái)灣和北京設(shè)立了四家預(yù)測(cè)試中心為客戶提供HDMI CT 測(cè)試以縮短客戶產(chǎn)品上市的時(shí)間。在本文中我們將討論HDMI CTS V.1.3新增加的一些重要內(nèi)容。同時(shí)我們也將著重總結(jié)一些典型測(cè)試項(xiàng)目失敗的原因和可能的修改方案。
標(biāo)簽： HDMI CTS 1.3 兼容測(cè)試
上傳時(shí)間： 2013-12-15
上傳用戶：古谷仁美
SL811開發(fā)資料_包含源程序_電路圖_芯片資料:SL811HS Embedded USB Host/Slave Controller.The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB peripherals. The SL811HS can interface to devices such as microprocessors, microcontrollers, DSPs, or directly to a variety of buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1.The SL811HS USB Host/Slave Controller incorporates USB Serial Interface functionality along with internal full-/low-speed transceivers.The SL811HS supports and operates in USB full-speed mode at 12 Mbps, or at low-speed 1.5-Mbps mode.The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support to allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUs and many others. Internally,the SL811HS contains a 256-byte RAM data buffer which is used for control registers and data buffer.The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages operate at 3.3 VDC. The I/O interface logic is 5V-tolerant.
上傳時(shí)間： 2013-12-22
上傳用戶：a82531317
ECHNICAL COMMITTEE No. 65: INDUSTRIAL-PROCESS MEASUREMENT AND CONTROL WORKING GROUP 6 VOTING DRAFT - PUBLICLY AVAILABLE Specification - FUNCTION BLOCKS FOR INDUSTRIAL-PROCESS MEASUREMENT AND CONTROL SYSTEMS
標(biāo)簽： INDUSTRIAL-PROCESS MEASUREMENT COMMITTEE ECHNICAL
上傳時(shí)間： 2014-10-28
上傳用戶：源弋弋
ECHNICAL COMMITTEE No. 65: INDUSTRIAL-PROCESS MEASUREMENT AND CONTROL WORKING GROUP 6 VOTING DRAFT - PUBLICLY AVAILABLE Specification - FUNCTION BLOCKS FOR INDUSTRIAL-PROCESS MEASUREMENT AND CONTROL SYSTEMS
標(biāo)簽： INDUSTRIAL-PROCESS MEASUREMENT COMMITTEE ECHNICAL
上傳時(shí)間： 2015-02-11
上傳用戶：baiom
ECHNICAL COMMITTEE No. 65: INDUSTRIAL-PROCESS MEASUREMENT AND CONTROL WORKING GROUP 6 VOTING DRAFT - PUBLICLY AVAILABLE Specification - FUNCTION BLOCKS FOR INDUSTRIAL-PROCESS MEASUREMENT AND CONTROL SYSTEMS
標(biāo)簽： INDUSTRIAL-PROCESS MEASUREMENT COMMITTEE ECHNICAL
上傳時(shí)間： 2013-12-27
上傳用戶：frank1234
OSERL (Open SMPP Erlang Library) is an erlang implementation of the Short Message Peer to Peer protocol, covering the entire Specification (version 5.0). Forward and backward compatibilities guidelines were adopted.
標(biāo)簽： Peer implementation Library Message
上傳時(shí)間： 2013-12-29
上傳用戶：dengzb84
Pocket SIP Messenger is a SIP instant messaging client for small devices that use Windows CE (iPAQ Pocket PC, ...). The IM protocol is based on SIMPLE (IETF) working group s Specification.
標(biāo)簽： Messenger SIP messaging instant
上傳時(shí)間： 2015-03-13
上傳用戶：lyy1234
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