Integrated EMI/Thermal Design forSwitching Power SuppliesWei ZhangThesis submitted to the Faculty of theVirginia Polytechnic Institute and State Universityin partial fulfillment of the requirements for the degree of
Integrated EMI/Thermal Design forSwitching Power SuppliesWei Zhang(ABSTRACT)This work presents the modeling and analysis of EMI and thermal performancefor switch power supply by using the CAD tools. The methodology and design guidelinesare developed.By using a boost PFC circuit as an example, an equivalent circuit model is builtfor EMI noise prediction and analysis. The parasitic elements of circuit layout andcomponents are extracted analytically or by using CAD tools. Based on the model, circuitlayout and magnetic component design are modified to minimize circuit EMI. EMI filtercan be designed at an early stage without prototype implementation.In the second part, thermal analyses are conducted for the circuit by using thesoftware Flotherm, which includes the mechanism of conduction, convection andradiation. Thermal models are built for the components. Thermal performance of thecircuit and the temperature profile of components are predicted. Improved thermalmanagement and winding arrangement are investigated to reduce temperature.In the third part, several circuit layouts and inductor design examples are checkedfrom both the EMI and thermal point of view. Insightful information is obtained.
The LTC®3562 quad output step-down regulator is designedfor multicore handheld microprocessor applications thatoperate from a single Li-Ion battery. Its four monolithic, higheffi ciency buck regulators support Intel’s mobile CPU P-Stateand C-State energy saving operating modes. The outputvoltages are independently controllable via I2C, and eachoutput can be independently started and shut down. Designerscan choose from power saving pulse-skipping mode orBurst Mode® operation, or select low noise LDO mode. Thespace-saving LTC3562 is available in a 3mm × 3mm QFNpackage and requires few external components.
Industrial remote monitoring systems and keep-alivecircuits spend most of their time in standby mode. Manyof these systems also depend on battery power, so powersupply effi ciency in standby state is very important tomaximize battery life. The LT®8410/-1 high effi ciencyboost converter is ideal for these systems, requiringonly 8.5μA of quiescent current in standby mode. Thedevice integrates high value (12.4M/0.4M) output feedbackresistors, signifi cantly reducing input current whenthe output is in regulation with no load. Other featuresinclude an integrated 40V switch and Schottky diode,output disconnect with current limit, built in soft-start,overvoltage protection and a wide input range, all in atiny 8-pin 2mm × 2mm DFN package.
The LTC3546 is a dual output current mode buck regulatorwith fl exible output current partitioning. Beyondthe advantages normally associated with dual outputregulators (reduced size, cost, EMI and part count, withimproved effi ciency), the LTC3546’s outputs can bepartitioned for either 3A and 1A outputs, or two 2A outputs.This increases its application range and simplifi esmultiple supply rail designs. A confi gurable Burst Mode®clamp for each output sets the current transition levelbetween Burst Mode operation and forced continuousconduction mode to optimize effi ciency over the entireoutput range. An adjustable switching frequency up to4MHz and internal power MOSFET switches allow forsmall and compact footprints.
該應(yīng)用報(bào)告描述了旋轉(zhuǎn)檢測器的實(shí)現(xiàn)，該旋轉(zhuǎn)檢測器使用一對(duì)可檢測磁場的巨磁阻GMR（Giant Magneto-Resistive,）傳感器。傳感器的分布使它們不使用正交信號(hào)序列，這提供了討論非正交情況如何配置SIF的機(jī)會(huì)。討論了調(diào)試SIF應(yīng)用程序的技術(shù)，提供了一個(gè)設(shè)計(jì)非正交進(jìn)程狀態(tài)機(jī)（processing state machines）的工具。
The CAT93C46 is a 1 kb Serial EEPROM memory device which isconfigured as either 64 registers of 16 bits (ORG pin at VCC) or 128registers of 8 bits (ORG pin at GND). Each register can be written (orread) serially by using the DI (or DO) pin. The CAT93C46 features aself−timed internal write with auto−clear. On−chip Power−On Resetcircuit protects the internal logic against powering up in the wrongstate.
The SN65LBC170 and SN75LBC170 aremonolithic integrated circuits designed forbidirectional data communication on multipointbus-transmission lines. Potential applicationsinclude serial or parallel data transmission, cabledperipheral buses with twin axial, ribbon, ortwisted-pair cabling. These devices are suitablefor FAST-20 SCSI and can transmit or receivedata pulses as short as 25 ns, with skew lessthan 3 ns.These devices combine three 3-state differentialline drivers and three differential input linereceivers, all of which operate from a single 5-Vpower supply.The driver differential outputs and the receiverdifferential inputs are connected internally to formthree differential input/output (I/O) bus ports thatare designed to offer minimum loading to the buswhenever the driver is disabled or VCC = 0. Theseports feature a wide common-mode voltage rangemaking the device suitable for party-lineapplications over long cable runs.
NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.
The PCA9516 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.While retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both the data(SDA) and the clock (SCL) lines, thus enabling five buses of 400 pF.The I2C-bus capacitance limit of 400 pF restricts the number ofdevices and bus length. Using the PCA9516 enables the systemdesigner to divide the bus into five segments off of a hub where anysegment to segment transition sees only one repeater delay.
The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
