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Step-vary

DAC技術(shù)用語 (D/A Converters Defini

Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full scale. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full Scale Error): The difference between theoutput voltage (or current) with full scale input code and theideal voltage (or current) that should exist with a full scale inputcode.Gain Temperature Coefficient (Full Scale TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full scale).Can be expressed as a percentage of full scale or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full scale voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.

標簽： Converters Defini DAC

上傳時間： 2013-10-30

上傳用戶：stvnash
PCB設(shè)計問題集錦

PCB設(shè)計問題集錦問：PCB圖中各種字符往往容易疊加在一起，或者相距很近，當(dāng)板子布得很密時，情況更加嚴重。當(dāng)我用Verify Design進行檢查時，會產(chǎn)生錯誤，但這種錯誤可以忽略。往往這種錯誤很多，有幾百個，將其他更重要的錯誤淹沒了，如何使Verify Design會略掉這種錯誤，或者在眾多的錯誤中快速找到重要的錯誤。　　　答：可以在顏色顯示中將文字去掉,不顯示后再檢查;并記錄錯誤數(shù)目。但一定要檢查是否真正屬于不需要的文字。問： What’s mean of below warning:(6230,8330 L1) Latium Rule not checked: COMPONENT U26 component rule.答：這是有關(guān)制造方面的一個檢查，您沒有相關(guān)設(shè)定，所以可以不檢查。問：怎樣導(dǎo)出jop文件？答：應(yīng)該是JOB文件吧？低版本的powerPCB與PADS使用JOB文件。現(xiàn)在只能輸出ASC文件，方法如下STEP：FILE/EXPORT/選擇一個asc名稱/選擇Select ALL/在Format下選擇合適的版本/在Unit下選Current比較好/點擊OK/完成然后在低版本的powerPCB與PADS產(chǎn)品中Import保存的ASC文件，再保存為JOB文件。問：怎樣導(dǎo)入reu文件？答：在ECO與Design 工具盒中都可以進行，分別打開ECO與Design 工具盒，點擊右邊第2個圖標就可以。問：為什么我在pad stacks中再設(shè)一個via:1(如附件）和默認的standardvi(如附件）在布線時V選擇1，怎么布線時按add via不能添加進去這是怎么回事，因為有時要使用兩種不同的過孔。答：PowerPCB中有多個VIA時需要在Design Rule下根據(jù)信號分別設(shè)置VIA的使用條件，如電源類只能用Standard VIA等等，這樣操作時就比較方便。詳細設(shè)置方法在PowerPCB軟件通中有介紹。問：為什么我把On-line DRC設(shè)置為prevent..移動元時就會彈出(圖2),而你們教程中也是這樣設(shè)置怎么不會呢?答：首先這不是錯誤,出現(xiàn)的原因是在數(shù)據(jù)中沒有BOARD OUTLINE.您可以設(shè)置一個,但是不使用它作為CAM輸出數(shù)據(jù). 問：我用ctrl+c復(fù)制線時怎設(shè)置原點進行復(fù)制，ctrl+v粘帖時總是以最下面一點和最左邊那一點為原點答：復(fù)制布線時與上面的MOVE MODE設(shè)置沒有任何關(guān)系,需要在右鍵菜單中選擇,這在PowerPCB軟件通教程中有專門介紹. 問：用(圖4)進行修改線時拉起時怎總是往左邊拉起(圖5)，不知有什么辦法可以輕易想拉起左就左，右就右。答：具體條件不明,請檢查一下您的DESIGN GRID,是否太大了. 問：好不容易拉起右邊但是用(圖6)修改線怎么改怎么下面都會有一條不能和在一起，而你教程里都會好好的(圖8)答：這可能還是與您的GRID 設(shè)置有關(guān),不過沒有問題,您可以將不需要的那段線刪除.最重要的是需要找到布線的感覺,每個軟件都不相同,所以需要多練習(xí)。問：尊敬的老師:您好！這個圖已經(jīng)畫好了，但我只對（如圖1）一種的完全間距進行檢查，怎么錯誤就那么多，不知怎么改進。請老師指點。這個圖在附件中請老師幫看一下，如果還有什么問題請指出來，本人在改進。謝！！！！！答：請注意您的DRC SETUP窗口下的設(shè)置是錯誤的,現(xiàn)在選中的SAME NET是對相同NET進行檢查,應(yīng)該選擇NET TO ALL.而不是SAME NET有關(guān)各項參數(shù)的含義請仔細閱讀第5部教程. 問： U101元件已建好，但元件框的拐角處不知是否正確，請幫忙CHECK 答：元件框等可以通過修改編輯來完成。問： U102和U103元件沒建完全，在自動建元件參數(shù)中有幾個不明白：如：SOIC--》silk screen欄下spacing from pin與outdent from first pin對應(yīng)U102和U103元件應(yīng)寫什么數(shù)值，還有這兩個元件SILK怎么自動設(shè)置，以及SILK內(nèi)有個圓圈怎么才能畫得與該元件參數(shù)一致。答：Spacing from pin指從PIN到SILK的Y方向的距離,outdent from first pin是第一PIN與SILK端點間的距離.請根據(jù)元件資料自己計算。

標簽： PCB 設(shè)計問題集錦

上傳時間： 2013-10-07

上傳用戶：comer1123
pdf轉(zhuǎn)cad軟件附pdf轉(zhuǎn)cad教程

附件為：pdf轉(zhuǎn)cad軟件最新版 PDF Fly V7.1安裝文件。還附有自制的Crack，把我的文件貼到裝好的目錄下就行了!沒有30天限制。附pdf轉(zhuǎn)cad軟件使用教程： 1、pdf轉(zhuǎn)cad軟件的界面比較簡單的，如下圖，點擊ADD添加你要轉(zhuǎn)換的PDF文件，然后下一步 2、選擇DXF格式，然后在右邊的option里面還可以進行相關(guān)的設(shè)置 3、然后再下一步。step 3頁面只要點最下面的 convert 就可以了轉(zhuǎn)完以后同樣線條沒有什么大問題的，只是文字肯定是被打碎的，你自己需要刪除后重新輸入要重新輸入。

標簽： cad 軟件教程

上傳時間： 2013-11-02

上傳用戶：asdstation
Using the TPS62150 as Step-Down LED Driver With Dimming

LED Dimmingcontrol

標簽： Step-Down Dimming Driver Using

上傳時間： 2014-01-26

上傳用戶：watch100
AX3514-V1 6資料

1.2MHz 2A Synchronous Step-Down converter

標簽： 3514 AX

上傳時間： 2013-11-01

上傳用戶：qingzhuhu
MAX16833高電壓,高亮度LED驅(qū)動器分部設(shè)計

Abstract: This application note details a step-by-step design process for the MAX16833 high-voltagehigh-brightness LED driver. This process can speed up prototyping and increase the chance for firstpass

標簽： 16833 MAX LED 高電壓

上傳時間： 2013-10-09

上傳用戶：tianjinfan
隔離電源設(shè)計手冊

Abstract: This document details the Oceanside (MAXREFDES9#) subsystem reference design, a 3.3V to 15V input,±15V (±12V) output, isolated power supply. The Oceanside design includes a high-efficiency step-up controller, a36V H-bridge transformer driver for isolated supplies, a wide input range, and adjustable output low-dropout linearregulator (LDO). Test results and hardware files are included.

標簽： 隔離電源設(shè)計手冊

上傳時間： 2013-10-12

上傳用戶：jinyao
電感開關(guān)穩(wěn)壓器提高輸入電壓

Abstract: Uses the MAX641 switching controller and an external discrete charge pump to step up the input voltage. This circuitcan service low loads and is efficient when the output is two, three, four times the input voltage. Adding the MAX627 MOSdriver can further increase the output current capability.

標簽： 電感開關(guān)穩(wěn)壓器輸入電壓

上傳時間： 2013-11-15

上傳用戶：zwei41
低電壓FPGA的高性能開關(guān)電源解決方案

The core voltages for FPGAs are moving lower as a resultof advances in the fabrication process. The newest FPGAfamily from Altera, the Stratix® II, now requires a corevoltage of 1.2V and the Stratix, Stratix GX, HardCopy®Stratix and CycloneTM families require a core voltage of1.5V. This article discusses how to power the core and I/Oof low voltage FPGAs using the latest step-down switchmode controllers from Linear Technology Corporation.

標簽： FPGA 低電壓高性能開關(guān) 電源解決方案

上傳時間： 2013-10-08

上傳用戶：wangfei22
100-15V TO 12V DCDC 原理圖 PCB BOM表

高的工作電壓高達100V N雙N溝道MOSFET同步驅(qū)動 The D810DCDC is a synchronous step-down switching regulator controller that can directly step-down voltages from up to 100V, making it ideal for telecom and automotive applications. The D810DCDC uses a constant on-time valley current control architecture to deliver very low duty cycles with accurate cycle-by-cycle current limit, without requiring a sense resistor. A precise internal reference provides 0.5% DC accuracy. A high bandwidth (25MHz) error amplifi er provides very fast line and load transient response. Large 1Ω gate drivers allow the D810DCDC to drive multiple MOSFETs for higher current applications. The operating frequency is selected by an external resistor and is compensated for variations in VIN and can also be synchronized to an external clock for switching-noise sensitive applications. Integrated bias control generates gate drive power from the input supply during start-up and when an output shortcircuit occurs, with the addition of a small external SOT23 MOSFET. When in regulation, power is derived from the output for higher effi ciency.

標簽： DCDC 100 12V BOM

上傳時間： 2013-10-24

上傳用戶：wd450412225