C51控制并口打印機(jī)實(shí)例：/* 沈陽新榮達(dá)電子 *//* 2004-12-7 */#include <reg52.h>#define uchar unsigned char#define uint unsigned int#define data_8 P0sbit BUSY = P1^2; //打印機(jī) BUSY 接P1.2sbit STB = P1^0; //打印機(jī) STB 接P1.0void print(uchar j) //打印子程序{ uchar i;while(BUSY){}; //BUSY=1，打印機(jī)忙，等待BUSY 為0 再發(fā)數(shù)data_8=j;STB=0;i++;i--;STB=1; //給出數(shù)據(jù)鎖存時(shí)鐘BUSY=1;}void main(void){BUSY = 1; //忙信號(hào)置高STB = 1; //選通信號(hào)置高print(0x1b); //打印機(jī)初始化命令print(0x38);print(0x04);for(;;){print(0xd0); //發(fā)送漢字內(nèi)碼“新榮達(dá)”print(0xc2);print(0xc8);print(0xd9);print(0xb4);print(0xef);print(0x0d); //換行}}
上傳時(shí)間： 2013-11-13
上傳用戶：lwq11
16 16點(diǎn)陣顯示漢字原理及顯示程序 #include "config.h" #define DOTLED_LINE_PORT PORTB #define DOTLED_LINE_DDR DDRB #define DOTLED_LINE_PIN PINB #define DOTLED_LINE_SCKT PB1 #define DOTLED_LINE_SCKH PB5 #define DOTLED_LINE_SDA PB3 #define DOTLED_ROW_PORT PORTC #define DOTLED_ROW_DDR DDRC #define DOTLED_ROW_PIN PINC #define DOTLED_ROW_A0 PC0 #define DOTLED_ROW_A1 PC1 #define DOTLED_ROW_A2 PC2 #define DOTLED_ROW_A3 PC3 #define DOTLED_ROW_E PC4 uint8 font[] = { /*-- 調(diào)入了一幅圖像：這是您新建的圖像 --*/ /*-- 寬度x高度=16x16 --*/ 0x00,0x00,0x00,0x00,0x08,0x38,0x18,0x44,0x08,0x44,0x08,0x04,0x08,0x08,0x08,0x10, 0x08,0x20,0x08,0x40,0x08,0x40,0x08,0x40,0x3E,0x7C,0x00,0x00,0x00,0x00,0x00,0x00 }; static void TransmitByte(uint8 byte); static void SelectRow(uint8 row); static void FlipLatchLine(void); static void TransmitByte(uint8 byte) { uint8 i; for(i = 0 ; i < 8 ; i ++) { if(byte & (1 << i)) { DOTLED_LINE_PORT |= _BV(DOTLED_LINE_SDA); } else { DOTLED_LINE_PORT &= ~_BV(DOTLED_LINE_SDA); } //__delay_cycles(100); DOTLED_LINE_PORT |= _BV(DOTLED_LINE_SCKH); //__delay_cycles(100); DOTLED_LINE_PORT &= ~_BV(DOTLED_LINE_SCKH); //__delay_cycles(100); } } static void SelectRow(uint8 row) { //row -= 1; row |= DOTLED_ROW_PIN & 0xe0; DOTLED_ROW_PORT = row; } static void FlipLatchLine(void) { DOTLED_LINE_PORT |= _BV(DOTLED_LINE_SCKT); DOTLED_LINE_PORT &= ~_BV(DOTLED_LINE_SCKT); } void InitDotLedPort(void) { DOTLED_LINE_PORT &= ~(_BV(DOTLED_LINE_SCKT) | _BV(DOTLED_LINE_SCKH)); DOTLED_LINE_PORT |= _BV(DOTLED_LINE_SDA); DOTLED_LINE_DDR |= _BV(DOTLED_LINE_SCKT) | _BV(DOTLED_LINE_SCKH) | _BV(DOTLED_LINE_SDA); DOTLED_ROW_PORT |= 0x1f; DOTLED_ROW_PORT &= 0xf0; DOTLED_ROW_DDR |= 0x1f; } void EnableRow(boolean IsEnable) { if(IsEnable) { DOTLED_ROW_PORT &= ~_BV(DOTLED_ROW_E); } else { DOTLED_ROW_PORT |= _BV(DOTLED_ROW_E); } } void PrintDotLed(uint8 * buffer) { uint8 i , tmp; for(i = 0 ; i < 16 ; i ++) { tmp = *buffer ++; TransmitByte(~tmp); tmp = *buffer ++; TransmitByte(~tmp); SelectRow(i); FlipLatchLine(); } } void main(void) { InitDotLedPort(); EnableRow(TRUE); while(1) { PrintDotLed(font); __delay_cycles(5000); } } //---------------------------------------------------- config.h文件 #ifndef _CONFIG_H #define _CONFIG_H //#define GCCAVR #define CPU_CYCLES 7372800L #ifndef GCCAVR #define _BV(bit) (1 << (bit)) #endif #define MSB 0x80 #define LSB 0x01 #define FALSE 0 #define TRUE 1 typedef unsigned char uint8; typedef unsigned int uint16; typedef unsigned long uint32; typedef unsigned char boolean; #include <ioavr.h> #include <inavr.h> #include "dotled.h" #endif //-----
標(biāo)簽： 16 點(diǎn)陣顯示 漢字 顯示程序
上傳時(shí)間： 2013-11-18
上傳用戶：mnacyf
51單片機(jī)驅(qū)動(dòng)步進(jìn)電機(jī)(含電路圖和源程序代碼） 源程序:stepper.c stepper.hex /* * STEPPER.C * sweeping stepper's rotor cw and cww 400 steps * Copyright (c) 1999 by W.Sirichote */ ＃i nclude c:\mc5151io.h /* include i/o header file */ ＃i nclude c:\mc5151reg.h register unsigned char j,flag1,temp; register unsigned int cw_n,ccw_n; unsigned char step[8]={0x80,0xc0,0x40,0x60,0x20,0x30,0x10,0x90} #define n 400 /* flag1 mask byte 0x01 run cw() 0x02 run ccw() */
標(biāo)簽： 51單片機(jī) 驅(qū)動(dòng) 步進(jìn)電機(jī) C語言
上傳時(shí)間： 2013-11-09
上傳用戶：釣鰲牧馬
C語言編程基礎(chǔ)：1. 十六進(jìn)制表示字節(jié)0x5a：二進(jìn)制為01011010B；0x6E為01101110。 2. 如果將一個(gè)16位二進(jìn)數(shù)賦給一個(gè)8位的字節(jié)變量，則自動(dòng)截?cái)酁榈?位，而丟掉高8位。 3. ++var表示對變量var先增一；var—表示對變量后減一。 4. x |= 0x0f;表示為 x = x | 0x0f; 5. TMOD = ( TMOD & 0xf0 ) | 0x05;表示給變量TMOD的低四位賦值0x5，而不改變TMOD的高四位。 6. While( 1 ); 表示無限執(zhí)行該語句，即死循環(huán)。語句后的分號(hào)表示空循環(huán)體，也就是{;} 在某引腳輸出高電平的編程方法：（比如P1.3（PIN4）引腳）1. #include <AT89x52.h> //該頭文檔中有單片機(jī)內(nèi)部資源的符號(hào)化定義，其中包含P1.3 2. void main( void ) //void 表示沒有輸入?yún)?shù)，也沒有函數(shù)返值，這入單片機(jī)運(yùn)行的復(fù)位入口 3. { 4. P1_3 = 1; //給P1_3賦值1，引腳P1.3就能輸出高電平VCC 5. While( 1 ); //死循環(huán)，相當(dāng) LOOP: goto LOOP; 6. } 注意：P0的每個(gè)引腳要輸出高電平時(shí)，必須外接上拉電阻（如4K7）至VCC電源。在某引腳輸出低電平的編程方法：（比如P2.7引腳）代碼1. #include <AT89x52.h> //該頭文檔中有單片機(jī)內(nèi)部資源的符號(hào)化定義，其中包含P2.7 2. void main( void ) //void 表示沒有輸入?yún)?shù)，也沒有函數(shù)返值，這入單片機(jī)運(yùn)行的復(fù)位入口 3. { 4. P2_7 = 0; //給P2_7賦值0，引腳P2.7就能輸出低電平GND 5. While( 1 ); //死循環(huán)，相當(dāng) LOOP: goto LOOP; 6. } 在某引腳輸出方波編程方法：（比如P3.1引腳）代碼1. #include <AT89x52.h> //該頭文檔中有單片機(jī)內(nèi)部資源的符號(hào)化定義，其中包含P3.1 2. void main( void ) //void 表示沒有輸入?yún)?shù)，也沒有函數(shù)返值，這入單片機(jī)運(yùn)行的復(fù)位入口 3. { 4. While( 1 ) //非零表示真，如果為真則執(zhí)行下面循環(huán)體的語句 5. { 6. P3_1 = 1; //給P3_1賦值1，引腳P3.1就能輸出高電平VCC 7. P3_1 = 0; //給P3_1賦值0，引腳P3.1就能輸出低電平GND 8. } //由于一直為真，所以不斷輸出高、低、高、低……，從而形成方波 9. } 將某引腳的輸入電平取反后，從另一個(gè)引腳輸出：（ 比如 P0.4 = NOT( P1.1) ）
標(biāo)簽： 51單片機(jī)C語言 編程實(shí)例
上傳時(shí)間： 2013-11-02
上傳用戶：zengduo
/* 4位8段數(shù)碼管分別動(dòng)態(tài)顯示“1234”， */ #include "7LEDShow.h" void main() { DIGPORT = 0; // 關(guān)閉顯示 TMOD = 0x01; // T0工作方式1 /* 2ms 定時(shí)設(shè)置 */ time0_tmp = 65536-time0*fosc/12; TH0 = (time0_tmp/256); TL0 = (time0_tmp%256); TR0 = 1; ET0 = 1; EA = 1; digbit = 0x01; // 從第一位數(shù)碼管開始
標(biāo)簽： 51單片機(jī)C語言 應(yīng)用程序
上傳時(shí)間： 2013-12-12
上傳用戶：kachleen
EEPROM為ATMEL公司的AT24C01A。單片機(jī)為ATMEL公司的AT89C51。2. 軟件說明 C語言為Franklin C V3.2。將源程序另存為testi2c.c，用命令C51 testi2c.cL51 TESTI2C.OBJOHS51 TESTI2C編譯，連接，得到TESTI2C.HEX文件，即可由編程器讀入并進(jìn)行寫片，實(shí)驗(yàn)。3．源程序#include <reg51.h>#include <intrins.h> #define uchar unsigned char#define uint unsigned int#define AddWr 0xa0 /*器件地址選擇及寫標(biāo)志*/#define AddRd 0xa1 /*器件地址選擇及讀標(biāo)志*/#define Hidden 0x0e /*顯示器的消隱碼*/
上傳時(shí)間： 2013-10-09
上傳用戶：hjshhyy
include "macrodefine.h"#include "lpc2294.h" //ADS1210初始化子程序void AD_Init(void){ Delayus(2); SPI1_Communation(0x64); SPI1_Communation(0x72); //單極性，SDOUT獨(dú)立，先MSB，REF使用內(nèi)部 SPI1_Communation(0x20); //自校準(zhǔn)模式，增益1，通道0 SPI1_Communation(0x87); //TURBO=16， SPI1_Communation(0xa0); //數(shù)據(jù)更新率100}//讀取ADS1210轉(zhuǎn)換結(jié)果子程序uint32 Read_AD_Data(void){ uint8 i=0; uint8 Data_Temp[3]; uint32 Result_HEX=0; Delayus(1); SPI1_Communation(0xc0); for(i=0;i<3;i++) { Data_Temp[i] =SPI1_Communation(0xff); }
上傳時(shí)間： 2013-10-10
上傳用戶：suicone
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
標(biāo)簽： FPGA 安全系統(tǒng)
上傳時(shí)間： 2013-11-05
上傳用戶：維子哥哥
Abstract: There are many things to consider when designing a power supply for a field-programmablegate array (FPGA). These include (but are not limited to) the high number of voltage rails, and thediffering requirements for both sequencing/tracking and the voltage ripple limits. This application noteexplains these and other power-supply considerations that an engineer must think through whendesigning a power supply for an FPGA.
上傳時(shí)間： 2013-11-10
上傳用戶：iswlkje
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