Providing power for the Pentium® microprocessor family isnot a trivial task by any means. In an effort to simplify thistask we have developed a new switching regulator controlcircuit and a new linear regulator to address the needs ofthese processors. Considerable time has been spent developingan optimized decoupling network. Here are severalcircuits using the new LTC®1266 Synchronous buck regulatorcontrol chip and the LT®1584 linear regulator toprovide power for Pentium processors and Pentium VREprocessors. The Pentium processor has a supply requirementof 3.3V ±5%. The Pentium VRE processor requires3.500V ±100mV.
在綜合分析諧波勵(lì)磁無刷同步發(fā)電機(jī)勵(lì)磁控制系統(tǒng)的基礎(chǔ)上,對(duì)其勵(lì)磁控制策略進(jìn)行了研究,開發(fā)了一套基于DSP( TMS320F2812) 控制的新型柴油發(fā)電機(jī)勵(lì)磁控制系統(tǒng),該系統(tǒng)采用參數(shù)自適應(yīng)模糊PID 控制勵(lì)磁,選用交流采樣方式實(shí)時(shí)檢測(cè)各信號(hào)的瞬時(shí)特性,系統(tǒng)仿真結(jié)果以及在1 臺(tái)25 kW 工頻柴油發(fā)電機(jī)上的試驗(yàn)結(jié)果證明了該控制器具有較好的電壓調(diào)節(jié)特性,系統(tǒng)穩(wěn)態(tài)和暫態(tài)性能完全滿足發(fā)電機(jī)對(duì)勵(lì)磁系統(tǒng)的要求。關(guān)鍵詞:勵(lì)磁調(diào)節(jié);模糊PID 控制;數(shù)字信號(hào)處理器;交流采樣
Abstract :According to the general analysis of the excitation cont rol system of the harmonious wave excitation brushless Synchronous generator and it s characteristics ,a new type of diesel generator excitation cont rol system based on DSP( TMS320F2812) was designed. An adaptive fuzzy PID cont rol of excitation is used in this system. To detect the t ransient characteristics of the signals in a timely manner ,AC sampling was applied.The system simulation result s and the testing result s f rom a 25 kW diesel generator (50 Hz) can prove that the voltage regulation characteristics of the excitation cont rol system are very well ,and both the steadyOstate performance and the t ransient performance of the generator are also good.Key words :excitation cont rol ;fuzzy PID cont rol ;digital signal processor (DSP) ;AC sampling
SDH[1](Synchronous Digital Hierarchy，同步數(shù)字體系)光端機(jī)容量較大，一般是16E1到4032E1。SDH是一種將復(fù)接、線路傳輸及交換功能融為一體、并由統(tǒng)一網(wǎng)管系統(tǒng)操作的綜合信息傳送網(wǎng)絡(luò)，是美國貝爾通信技術(shù)研究所提出來的同步光網(wǎng)絡(luò)(SONET)。
This Application Note covers the basics of how to use Verilog as applied to ComplexProgrammable Logic Devices. Various combinational logic circuit examples, such asmultiplexers, decoders, encoders, comparators and adders are provided. Synchronous logiccircuit examples, such as counters and state machines are also provided.
This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design includes the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully Synchronous interface through the ce, clk,and rst ports.
A client/server application that implements the game of BINGO. This example broadcasts information via a multicast socket, builds its GUI with Swing components, uses multiple Synchronous threads, and communicates with RMI.
VHDL 關(guān)于2DFFT設(shè)計(jì)程序
u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be
seen in the following section.
u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus
network, and it support these sub-modules scinode1∼ scinode9 reset and clk
and global_cnt signals to Synchronous the sub-modules to simplify the overall
design.
u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation
result.
u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow
situation.
一個(gè)簡單的ＳＰＩ ＩＰ核，SPI Core Specifications 可以從說明文檔中找到！
The simple Serial Peripheral Interface core is an enhanced version of the Serial Peripheral Interface found on Motorola s M68HC11 family of CPUs. The Serial Peripheral Interface is a serial, Synchronous communication protocol that requires a minimum of 3 wires.
FEATURES:
· Compatible with Motorola’s SPI specifications
· Enhanced M68HC11 Serial Peripheral Interface
· 4 entries deep read FIFO
· 4 entries deep write FIFO
· Interrupt generation after 1, 2, 3, or 4 transferred bytes
· 8 bit WISHBONE RevB.3 Classic interface
· Operates from a wide range of input clock frequencies
· Static Synchronous design
· Fully synthesizable
