Verilog and VHDL狀態機設計，英文pdf格式
State machine design techniques for Verilog and VHDL
Abstract : Designing a Synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in
engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding
presented. Different methodologies will be compared using real-world examples.
Pipeline synchronization is a simple, low-cost, highbandwidth,highreliability solution to interfaces between Synchronous and aSynchronous systems, or between
Synchronous systems operating from different clocks.
This paper presents several low-latency mixed-timing
FIFO (first-in–first-out) interfaces designs that interface systems
on a chip working at different speeds. The connected systems
can be either Synchronous or aSynchronous. The designs are then
adapted to work between systems with very long interconnect
delays, by migrating a single-clock solution by Carloni et al.
(1999, 2000, and 2001) (for “latency-insensitive” protocols) to
mixed-timing domains. The new designs can be made arbitrarily
robust with regard to metastability and interface operating speeds.
Initial simulations for both latency and throughput are promising.
Ideal for large low power (nanoWatt) and connectivity applications that benefit from the availability of four serial ports: double Synchronous serial ports (I² C™ and SPI™ ) and double aSynchronous (LIN capable) serial ports. Large amounts of RAM memory for buffering and FLASH program memory make it ideal for instrumentation panels, TCP/IP enabled embedded applications as well as metering and industrial control and monitoring applications. While operating up to 40 MHz, it is also backward software and hardware compatible with the PIC18F8720.
vhdl編寫，8b—10b 編解碼器設計
Encoder:
8b/10b Encoder (file: 8b10b_enc.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
8-bit parallel unencoded data input
KI input selects data or control encoding
ASynchronous active high reset initializes all logic
Encoded data output
10-bit parallel encoded output valid 1 clock later
Decoder:
8b/10b Decoder (file: 8b10b_dec.vhd)
Synchronous clocked inputs (latched on each clock rising edge)
10-bit parallel encoded data input
ASynchronous active high reset initializes all logic
Decoded data, disparity and KO outputs
8-bit parallel unencoded output valid 1 clock later
The module includes three sub_module:FDivider128,generates the 1/128 frequency, MD_Counter8Zero, generates the flute when the posedge, MD_Counter8One,generates the flute when the negedge.The aim of the module is to generate the mended miller code to be the source of the MillerDecode.
輸入的數據以下降沿采樣，有效輸入范圍為上升沿前一點，輸入數據包括1 b0+有效數據+1 b0
Operating Rule: R_DATAUNCODE must be Synchronous with R_ACTIVE
This paper presents a low-power aSynchronous implementation of the 80C51 microcontroller. It was realized in a 0.5 µ m CMOS process and it shows a power advantage of a factor 4 compared to a recent Synchronous implementation in the same technology. The chip is fully bit compatible with the Synchronous implementation, and timing compatible for external memory access. The circuit is a compiled VLSI-program, using Tangram as VLSI-programming language and the Tangram tool set to compile the design automatically to a standard-cell netlist. This design approach proves to be powerful enough to describe the microcontroller and derive an efficient implementation. Further, it offers the designer the possibility to explore various alternatives in the design space.
-- DESCRIPTION : Shift register
-- Type : univ
-- Width : 4
-- Shift direction: right/left (right active high)
--
-- CLK active : high
-- CLR active : high
-- CLR type : Synchronous
-- SET active : high
-- SET type : Synchronous
-- LOAD active : high
-- CE active : high
-- SERIAL input : SI
CRC碼產生器與校驗器程序
Features ：
Executes in one clock cycle per data word
Any polynomial from 4 to 32 bits
Any data width from 1 to 256 bits
Any initialization value
Synchronous or aSynchronous reset
In this project we analyze and design the minimum mean-square error (MMSE) multiuser receiver for uniformly quantized Synchronous code division multiple access (CDMA) signals in additive white Gaussian noise (AWGN) channels.This project is mainly based on the representation of uniform quantizer by gain plus additive noise model. Based on this model, we derive the weight vector and the output signal-to-interference ratio (SIR) of the MMSE receiver. The effects of quantization on the MMSE receiver performance is characterized in a single parameter named 鈥漞quivalent noise variance鈥? The optimal quantizer stepsize which maximizes the MMSE receiver output SNR is also determined.
