我自己寫的vhdl程序，內(nèi)有畫圖器，ram 和控制ram。還有TEST bentch。
上傳時間： 2014-01-23
上傳用戶：黑漆漆
The purpose of this lab is to introduce the concept of FSMs with a datapath, and to study the usage of more complex TEST benches. Also, we enforce a rudimentary design methodology by assuming that the students are part of a bigger project, and have no knowledge of VHDL-implementation of the datapath (made by a hypothetical other group) other than its predefined Entity Interface until they come to the lab. The rest of this document is structured as follows: Section 2 describes some prelimi- nary reading and exercises that should be done before the lab. Section 3 details the design tasks that should be carried out to pass this lab.
標(biāo)簽： introduce datapath purpose concept
上傳時間： 2014-01-24
上傳用戶：熊少鋒
本程序是MP3的解碼程序，可以用VC編譯或者用GNU編譯，可以運行在PC機上。 本程可以MP3文件解壓為WAV文件 TEST 中的代碼可以播放WAV文件 有興趣的朋友可以把這段mp3程序移植到開發(fā)板上，這樣就可以用開發(fā)板播放MP3了。
上傳時間： 2014-01-06
上傳用戶：songrui
UCOS/II for ICCAVR - The version of UCOS/II is 2.04 - the original port was done by Ole Saether for the IAR compiler. Jens E. Holtegaard ported one version using ICCAVR. Joerg Meyer did another port (using Jens port as a start?). This is basically Joerg s port plus a little bit of changes and documentation by me. - YOU MUST DOWNLOAD THE MAIN PART OF THE UCOS/II FROM THE UCOS/II WEBSITE http://www.ucos-ii.com . The supplied project file assumes the portable source is in the ..\source directory. - Joerg has written couple document showing the stack frames etc. but it is in German :-) They are included in this directory. - The Timer2 overflow interrupt is used for Timer Tick. If you want to change that, modify os_cpu_c.c and os_cpu_a.s - I have TESTed this using ATMega103 with and without external RAM using AVR Studio simulator. See TEST1.c TEST program. Both Code Compressed (PRO) and STD versions have been TESTed.
標(biāo)簽： UCOS original Saether version
上傳時間： 2015-11-14
上傳用戶：ippler8
This Source.zip has three application code folders containing .java and .class files and two .jar files as follows: 1. desktop-side_JXTA4JMS 2. mobile-side_JXTA4JMS 3. JMS TEST Client 4. Listener.jar 5. JMSTESTClient.jar We now explain execution steps, we followed, to run this JXTA4JMS application. Before we try we require Application softwares and need to configure JXTA relay and J2EE server.
標(biāo)簽： application containing and folders
上傳時間： 2014-11-17
上傳用戶：z1191176801
Universal Serial Bus Implementers Forum Full and Low Speed Electrical and Interoperability Compliance TEST Procedure
標(biāo)簽： Interoperability Implementers Electrical Universal
上傳時間： 2015-11-18
上傳用戶：cc1915
In addition to individual algorithm, Demonstration System is a "data structure" (C language version) book algorithm corresponding to the code (CPP) and the TEST operating procedures (VC + +6.0 to the EXE). Through the system can demonstrate that the algorithm source code and operating results
標(biāo)簽： Demonstration individual algorithm structure
上傳時間： 2013-12-24
上傳用戶：change0329
Software TESTing, Second Edition provides practical insight into the world of software TESTing and quality assurance. Learn how to find problems in any computer program, how to plan an effective TEST approach and how to tell when software is ready for release. Updated from the previous edition in 2000 to include a chapter that specifically deals with TESTing software for security bugs, the processes and techniques used throughout the book are timeless. This book is an excellent investment if you want to better understand what your Software TEST team does or you want to write better software.
標(biāo)簽： practical Software provides software
上傳時間： 2014-08-01
上傳用戶：zhaiyanzhong
linux filesystem bootdisk-howto.This document describes how to design and build boot/root diskettes for Linux. These disks can be used as rescue disks or to TEST new system components. You should be reasonably familiar with system administration tasks before attempting to build a bootdisk. If you just want a rescue disk to have for emergencies,
標(biāo)簽： bootdisk-howto filesystem describes diskettes
上傳時間： 2015-11-22
上傳用戶：wanghui2438
This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the TEST bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
標(biāo)簽： Development Startix2 tailored Altera
上傳時間： 2014-01-19
上傳用戶：chongcongying
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