第一步，拿到一塊PCB，首先在紙上記錄好所有元?dú)饧男吞?hào)，參數(shù)，以及位置，尤其是二極管，三極管的方向，IC缺口的方向。最好用數(shù)碼相機(jī)拍兩張?jiān)獨(dú)饧恢玫恼掌? 第二步，拆掉所有器件，并且將PAD孔里的錫去掉。用酒精將PCB清洗干凈，然后放入掃描儀內(nèi)，啟動(dòng)POHTOSHOP，用彩色方式將絲印面掃入，并打印出來(lái)備用。 第三步，用水紗紙將TOP LAYER 和BOTTOM LAYER兩層輕微打磨，打磨到銅膜發(fā)亮，放入掃描儀，啟動(dòng)PHOTOSHOP，用彩色方式將兩層分別掃入。注意，PCB在掃描儀內(nèi)擺放一定要橫平樹(shù)直，否則掃描的圖象就無(wú)法使用，掃描儀分辨率請(qǐng)選為600。 需要的朋友請(qǐng)下載哦！
上傳時(shí)間： 2014-03-04
上傳用戶(hù)：tianming222
MP3 portable players are the trend in music-listening technology. These players do not includeany mechanical movements, thereby making them ideal for listening to music during any type ofactivity. MP3 is a digital compression technique based on MPEG Layer 3 which stores music ina lot less space than current CD technology. Software is readily available to create MP3 filesfrom an existing CD, and the user can then download these files into a portable MP3 player tobe enjoyed in almost any environment.
上傳時(shí)間： 2013-11-23
上傳用戶(hù)：nanxia
第一步，拿到一塊PCB，首先在紙上記錄好所有元?dú)饧男吞?hào)，參數(shù)，以及位置，尤其是二極管，三機(jī)管的方向，IC缺口的方向。最好用數(shù)碼相機(jī)拍兩張?jiān)獨(dú)饧恢玫恼掌５诙剑鸬羲衅骷⑶覍AD孔里的錫去掉。用酒精將PCB清洗干凈，然后放入掃描儀內(nèi)，啟動(dòng)POHTOSHOP，用彩色方式將絲印面掃入，并打印出來(lái)備用。第三步，用水紗紙將TOP LAYER 和BOTTOM LAYER兩層輕微打磨，打磨到銅膜發(fā)亮，放入掃描儀，啟動(dòng)PHOTOSHOP，用彩色方式將兩層分別掃入。注意，PCB在掃描儀內(nèi)擺放一定要橫平樹(shù)直，否則掃描的圖象就無(wú)法使用。第四步，調(diào)整畫(huà)布的對(duì)比度，明暗度，使有銅膜的部分和沒(méi)有銅膜的部分對(duì)比強(qiáng)烈，然后將次圖轉(zhuǎn)為黑白色，檢查線(xiàn)條是否清晰，如果不清晰，則重復(fù)本步驟。如果清晰，將圖存為黑白BMP格式文件TOP.BMP和BOT.BMP。第五步，將兩個(gè)BMP格式的文件分別轉(zhuǎn)為PROTEL格式文件，在PROTEL中調(diào)入兩層，如過(guò)兩層的PAD和VIA的位置基本重合，表明前幾個(gè)步驟做的很好，如果有偏差，則重復(fù)第三步。第六，將TOP。BMP轉(zhuǎn)化為T(mén)OP。PCB，注意要轉(zhuǎn)化到SILK層，就是黃色的那層，然后你在TOP層描線(xiàn)就是了，并且根據(jù)第二步的圖紙放置器件。畫(huà)完后將SILK層刪掉。 第七步，將BOT。BMP轉(zhuǎn)化為BOT。PCB，注意要轉(zhuǎn)化到SILK層，就是黃色的那層，然后你在BOT層描線(xiàn)就是了。畫(huà)完后將SILK層刪掉。第八步，在PROTEL中將TOP。PCB和BOT。PCB調(diào)入，合為一個(gè)圖就OK了。第九步，用激光打印機(jī)將TOP LAYER， BOTTOM LAYER分別打印到透明膠片上（1：1的比例），把膠片放到那塊PCB上，比較一下是否有誤，如果沒(méi)錯(cuò)，你就大功告成了。
上傳時(shí)間： 2013-11-24
上傳用戶(hù)：ynzfm
PCB LAYOUT 術(shù)語(yǔ)解釋(TERMS)1. COMPONENT SIDE(零件面、正面)︰大多數(shù)零件放置之面。2. SOLDER SIDE(焊錫面、反面)。3. SOLDER MASK(止焊膜面)︰通常指Solder Mask Open 之意。4. TOP PAD︰在零件面上所設(shè)計(jì)之零件腳PAD，不管是否鑽孔、電鍍。5. BOTTOM PAD：在銲錫面上所設(shè)計(jì)之零件腳PAD，不管是否鑽孔、電鍍。6. POSITIVE LAYER：?jiǎn)巍㈦p層板之各層線(xiàn)路；多層板之上、下兩層線(xiàn)路及內(nèi)層走線(xiàn)皆屬之。7. NEGATIVE LAYER：通常指多層板之電源層。8. INNER PAD：多層板之POSITIVE LAYER 內(nèi)層PAD。9. ANTI-PAD：多層板之NEGATIVE LAYER 上所使用之絕緣範(fàn)圍，不與零件腳相接。10. THERMAL PAD：多層板內(nèi)NEGATIVE LAYER 上必須零件腳時(shí)所使用之PAD，一般稱(chēng)為散熱孔或?qū)住?1. PAD (銲墊)：除了SMD PAD 外，其他PAD 之TOP PAD、BOTTOM PAD 及INNER PAD 之形狀大小皆應(yīng)相同。12. Moat : 不同信號(hào)的 Power& GND plane 之間的分隔線(xiàn)13. Grid : 佈線(xiàn)時(shí)的走線(xiàn)格點(diǎn)2. Test Point : ATE 測(cè)試點(diǎn)供工廠(chǎng)ICT 測(cè)試治具使用ICT 測(cè)試點(diǎn) LAYOUT 注意事項(xiàng):PCB 的每條TRACE 都要有一個(gè)作為測(cè)試用之TEST PAD(測(cè)試點(diǎn))，其原則如下：1. 一般測(cè)試點(diǎn)大小均為30-35mil，元件分布較密時(shí)，測(cè)試點(diǎn)最小可至30mil.測(cè)試點(diǎn)與元件PAD 的距離最小為40mil。2. 測(cè)試點(diǎn)與測(cè)試點(diǎn)間的間距最小為50-75mil，一般使用75mil。密度高時(shí)可使用50mil,3. 測(cè)試點(diǎn)必須均勻分佈於PCB 上，避免測(cè)試時(shí)造成板面受力不均。4. 多層板必須透過(guò)貫穿孔(VIA)將測(cè)試點(diǎn)留於錫爐著錫面上(Solder Side)。5. 測(cè)試點(diǎn)必需放至於Bottom Layer6. 輸出test point report(.asc 檔案powerpcb v3.5)供廠(chǎng)商分析可測(cè)率7. 測(cè)試點(diǎn)設(shè)置處:Setuppadsstacks
標(biāo)簽： layout design pcb 硬件工程師
上傳時(shí)間： 2013-11-17
上傳用戶(hù)：cjf0304
LAYOUT REPORT .............. 1 目錄.................. 1 1. PCB LAYOUT 術(shù)語(yǔ)解釋(TERMS)......... 2 2. Test Point : ATE 測(cè)試點(diǎn)供工廠(chǎng)ICT 測(cè)試治具使用............ 2 3. 基準(zhǔn)點(diǎn) (光學(xué)點(diǎn)) -for SMD:........... 4 4. 標(biāo)記 (LABEL ING)......... 5 5. VIA HOLE PAD................. 5 6. PCB Layer 排列方式...... 5 7.零件佈置注意事項(xiàng) (PLACEMENT NOTES)............... 5 8. PCB LAYOUT 設(shè)計(jì)............ 6 9. Transmission Line ( 傳輸線(xiàn) )..... 8 10.General Guidelines – 跨Plane.. 8 11. General Guidelines – 繞線(xiàn)....... 9 12. General Guidelines – Damping Resistor. 10 13. General Guidelines - RJ45 to Transformer................. 10 14. Clock Routing Guideline........... 12 15. OSC & CRYSTAL Guideline........... 12 16. CPU
上傳時(shí)間： 2013-10-29
上傳用戶(hù)：1234xhb
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2014-01-24
上傳用戶(hù)：s363994250
The ability to create groups of reports, and grant users access to reports by group. The ability to generate reports as PDF, XLS, HTML, and CSV files. The ability to generate bar, pie and xy charts for inclusion in reports. The ability to schedule and email PDF, XLS, and CSV reports. The ability to define reusable report parameters. Available parameter types include Date, Text, and Query Parameters. The ability to create multiple DataSources for use in generating reports. Support for JNDI DataSources and internal connection pooling via Commons-DBCP is included. The ability to upload and hot deploy new reports. Web based administration of users, groups, reports, parameters, and datasources. Cross platform database support via Hibernate based persistence layer. Available in a preconfigured bundle with Apache Tomcat.
標(biāo)簽： ability reports The to
上傳時(shí)間： 2014-01-14
上傳用戶(hù)：franktu
total是最后的版本。包括的全是最新的物理層和數(shù)據(jù)鏈路層。另外還有pro1和pro2的打包程序和調(diào)用它們形成的各自的界面程序，以及最后調(diào)用各個(gè)界面形成的總界面程序。由于時(shí)間匆忙，對(duì)數(shù)據(jù)鏈路層協(xié)議的界面化工作只做到了pro2，總界面上已經(jīng)留了所有6個(gè)程序的地方。PhysicalLayer包中包含了所有的物理層的程序的版本，以及它們各自的演示程序(一般為Physical)及打包程序(一般為PhyLayer)。顯示了整個(gè)物理層編寫(xiě)及修改演化的過(guò)程，僅供參考。Datalink Layer包中包含了數(shù)據(jù)鏈路層程序的各個(gè)版本。包含數(shù)據(jù)鏈路層基本操作模塊(Datalink.java)及各個(gè)協(xié)議的版本(pro1-pro3)。以及它們各自的演示程序及打包程序。顯示了整個(gè)物理層編寫(xiě)及修改演化的過(guò)程，僅供參考。運(yùn)行方法：只需要Java的運(yùn)行環(huán)境。先要預(yù)裝java，這里使用的是java的j2sdk-1_4_2_01-windows-i586版本。最新的1.5.0應(yīng)該也支持。采用的編譯器是Jcreator，其他的編譯器也應(yīng)該是可以用的。
上傳時(shí)間： 2013-12-19
上傳用戶(hù)：奇奇奔奔
一個(gè)mp3的解碼程序，c語(yǔ)言實(shí)現(xiàn)。其中只對(duì)layer III 進(jìn)行解碼。
上傳時(shí)間： 2014-01-01
上傳用戶(hù)：gxf2016
自適應(yīng)(Adaptive)神經(jīng)網(wǎng)絡(luò)源程序 The adaptive Neural Network Library is a collection of blocks that implement several Adaptive Neural Networks featuring different adaptation algorithms.~..~ There are 11 blocks that implement basically these 5 kinds of neural networks: 1) Adaptive Linear Network (ADALINE) 2) Multilayer Layer Perceptron with Extended Backpropagation algorithm (EBPA) 3) Radial Basis Functions (RBF) Networks 4) RBF Networks with Extended Minimal Resource Allocating algorithm (EMRAN) 5) RBF and Piecewise Linear Networks with Dynamic Cell Structure (DCS) algorithm A simulink example regarding the approximation of a scalar nonlinear function of 4 variables
標(biāo)簽： collection implement Adaptive adaptive
上傳時(shí)間： 2015-04-09
上傳用戶(hù)：ywqaxiwang
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
