鎖定放大是微弱信號檢測的重要手段。基于相關(guān)檢測理論，利用開關(guān)電容的開關(guān)實(shí)現(xiàn)鎖定放大器中乘法器的功能，提出開關(guān)電容和積分器相結(jié)合以實(shí)現(xiàn)相關(guān)檢測的方法，并設(shè)計出一種鎖定放大器。該鎖定放大器將微弱信號轉(zhuǎn)化為與之相關(guān)的方波，通過后續(xù)電路得到正比于被測信號的直流電平，為后續(xù)采集處理提供方便。測量數(shù)據(jù)表明鎖定放大器前級可將10-6 A的電流轉(zhuǎn)換為10-1 V的電壓，后級通過帶通濾波器級聯(lián)可將信號放大1×105倍。該方法在降低噪聲的同時，可對微弱信號進(jìn)行放大，線性度較高、穩(wěn)定性較好。 Abstract: Lock-in Amplifying（LIA）is one of important means for weak signal detection. Based on cross-correlation detection theory， switch in the swithched capacitor was used as multiplier of LIA， and a new method of correlation detection was proposed combining swithched capacitor with integrator. A kind of LIA was designed which can convert the weak signal to square-wave， then DC proportional to measured signal was obtained through follow-up conditioning circuit， providing convenience for signal acquisition and processing. The measured data shows that the electric current（10-6 A） can be changed into voltage（10-1 V） by LIA， and the signal is magnified 1×105 times by cascade band-pass filter. The noise is suppressed and the weak signal is amplified. It has the advantages of good linearity and stability.
標(biāo)簽： 開關(guān)電容 鎖定放大器
上傳時間： 2013-11-29
上傳用戶：黑漆漆
Abstract: This application note explains the hardware of different types of 1-Wire® interfaces and software examples adapted to this hardware with a focus on serial ports. Depending on the types of iButtons required for a project and the type of computer to be used, the most economical interface is easily found. The hardware examples shown are basically two different types: 5V general interface and 12V RS-232 interface. Within the 5V group a common printed circuit board could be used for all circuits described. The variations can be achieved by different populations of components. The same principal is used for the 12V RS-232 interface. The population determines if it is a Read all or a Read/Write all type of interface. There are other possible circuit implementations to create a 1-Wire interface. The circuits described in this application note cover many different configurations. For a custom application, one of the described options can be adapted to meet individual needs.
標(biāo)簽： iButtons Reading Writing and
上傳時間： 2013-10-29
上傳用戶：long14578
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-21
上傳用戶：wxqman
DBSCAN Designed by Dr. Michal aszykowski Department of Chemometrics Institute of Chemistry, The University of Silesia. It s the basic one.
標(biāo)簽： Chemometrics Department aszykowski Chemistry
上傳時間： 2015-03-29
上傳用戶：klin3139
算法ebook(10部算法經(jīng)典著作的合集) 算法ebook> 10部算法經(jīng)典著作的合集 chm格式 (1)Fundamentals of Data Structures by Ellis Horowitz and Sartaj Sahni (2)Data Structures, Algorithms and Program Style Using C by James F. Korsh and Leonard J. Garrett (3)Data Structures and Algorithm Analysis in C by Mark Allen Weiss (4)Data Structures: From Arrays to Priority Queues by Wayne Amsbury (5)Information Retrieval: Data Structures & Algorithms edited by William B. Frakes and Ricardo Baeza-Yates (6)Introduction to Algorithms by Thomas H. Cormen, Charles E. Leiserson, and Ronald L. Rivest (7)Practical Data Structures in C++ by Bryan Flamig (8)Reliable Data Structures in C by Thomas Plum (9)Data Structures and Algorithms Alfred V. Aho, Bell Laboratories, Murray Hill, New Jersey John E. Hopcroft, Cornell University, Ithaca, New York Jeffrey D. Ullman, Stanford University, Stanford, California (10)DDJ Algorithms and Data Structures Articles
標(biāo)簽： ebook Fundamentals Structures Ellis
上傳時間： 2015-04-04
上傳用戶：tfyt
The Art of Assembly Language Amazing! You’re actually reading this. That puts you into one of three categories: a student who is being forced to read this stuff for a class, someone who picked up this book by accident (probably because you have yet to be indoctrinated by the world at large), or one of the few who actually have an interest in learning assembly language.
標(biāo)簽： Assembly Language actually Amazing
上傳時間： 2015-04-30
上傳用戶：asddsd
JBoss, one of the leading java Open Source groups, integrates and develops these services for a full J2EE-based implementation. JBoss provides JBossServer, the basic EJB container, and Java Manage Preface 18 Great Events of the Twentieth Centuryment Extension (JMX) infrastructure. It also provides JBossMQ, for JMS messaging, JBossTX, for JTA/JTS transactions, JBossCMP for CMP persistence, JBossSX for JAAS based security, and JBossCX for JCA connectivity. Support for web components, such as servlets and JSP pages, is providedby an abstract integration layer. Implementations of the integration service are provided for third party servlet engines like Tomcat and Jetty. JBoss enables you to mix and match these components through JMX by replacing any component you want with a JMX compliant implementation for the same APIs.
標(biāo)簽： integrates develops services leading
上傳時間： 2014-11-03
上傳用戶：wsf950131
This book provides information about the concepts and procedures needed by a developer of messaging applications in a Sun™ ONE Message Queue (MQ) environment. This preface contains the following sections: • Audience for This Guide • Organization of This Guide • Conventions • Other Documentation Resources
標(biāo)簽： information procedures developer messaging
上傳時間： 2013-12-14
上傳用戶：netwolf
THIS is really two books in one: a tutorial and a reference manual for JDBC, the application programming interface that makes it possible for programmers to access databases from Java. The goal is to be useful to a wide range of readers, from database novices to database experts. Therefore, we have arranged the book so that information needed only by experts is separated out from the basic material. We hope that driver developers as well as application programmers and MIS administrators will find what they need. Because different sections are aimed at different audiences, we expect that few people will read every page. We have sometimes duplicated explanations in an effort to make reading easier for those who do not read all sections. This book will be most helpful to those who have some knowledge of the Java programming language and SQL (Structured Query Language), but one doesn t need to be an expert in either to understand the basic concepts presented here.
標(biāo)簽： application reference tutorial program
上傳時間： 2015-08-04
上傳用戶：zhengzg
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