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VHD

VHDl編寫

VHDl編寫，8b—10b 編解碼器設計 Encoder: 8b/10b Encoder (file: 8b10b_enc.VHD) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.VHD) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later

標簽： VHDl 編寫

上傳時間： 2016-05-05

上傳用戶：gundamwzc
在FPGA的嵌入式picoblaze設計中使用到的匯編器

在FPGA的嵌入式picoblaze設計中使用到的匯編器，在DOS下就可方便使用，方法：首先進行DOS命令窗，進行工作目錄，運行kcpsm3 <filename>.psm 編譯通過將生成VHD文件

標簽： picoblaze FPGA 嵌入式匯編器

上傳時間： 2016-06-27

上傳用戶：sammi
四位十進制頻率計設計包含測頻控制器（TESTCTL）

四位十進制頻率計設計包含測頻控制器（TESTCTL），4位鎖存器(REG4B)，十進制計數器（CNT10）的原程序(VHD)，波形文件(wmf ),包裝后的元件(bsf)。頂層原理圖文件（Block1.bdf）和波形。

標簽： TESTCTL 十進制頻率計設測頻

上傳時間： 2016-11-21

上傳用戶：lijianyu172
交通燈控制器編碼

交通燈控制器編碼，源描述的編譯順序tlc.VHD，est_vector.VHD

標簽： 交通燈控制器編碼

上傳時間： 2014-01-07

上傳用戶：海陸空653
空調系統有限狀態自動機編碼

空調系統有限狀態自動機編碼，各個源描述的編譯順序conditioner.VHD，conditioner_stim.VHD

標簽： 空調系統狀態自動機編碼

上傳時間： 2013-12-09

上傳用戶：watch100
是codic算法實現atan的virilog程序

是codic算法實現atan的virilog程序，模塊結構如下：Core Structure: sc_corproc.VHD->p2r_cordic.VHD->p2r_cordicpipe.VHD

標簽： virilog codic atan 算法

上傳時間： 2017-02-01

上傳用戶：waizhang
The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontro

The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontroller. It is not, and is not intended as, a high fidelity circuit simulation. This package includes the following files. Note that the license agreement is stated in the main VHDL file, PICCPU.VHD and common questions are answered in the file SYNTHPIC.TXT Files: README.TXT This file.. SYNTHPIC.TXT Questions and Answers PICCPU.VHD Main processor VHDL file PICALU.VHD ALU for the PICCPU PICREGS.VHD Data memory PICROM.VHD Program memory (created by HEX2VHDL utility) PICTEST.VHD Simple test bench I used to do testing (optional) PICTEST.CMD My Viewlogic ViewSim command file (again, optional) TEST1.ASM First program I assembled and ran on it. TEST2.ASM Another test program.. TEST3.ASM Yet another.. TEST4.ASM Yet another.. TEST5.ASM Yet another.. TEST6.ASM Yet another.. HEX2VHDL.CPP Utility for converting

標簽： synthesizable microcontro Synthetic PIC

上傳時間： 2013-12-22

上傳用戶：妄想演繹師
Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level circuits: sv_chip0.VHD, sv_chip1.VHD, sv_chip2.VHD and sv_chip3.VHD each of them built by one Virtex2000E fpga chip. This design is hierarchical and the sub-circuits can be used as smaller benchmarks.

標簽： Stereo-Vision description Darabiha contains

上傳時間： 2017-03-19

上傳用戶：comua
Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested i

Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .VHD - to display at 7 sgement display - D4to7 .VHD - Convert HEX decimal to ASCII code.

標簽： Transmitter controller Receiver Working

上傳時間： 2013-12-27

上傳用戶：541657925
此文件為EDA的8位分頻器

此文件為EDA的8位分頻器，但可以用于不同位分頻器，如：1位到10位等，用Quartus軟件來，以文件VHD格式編譯即可

標簽： EDA 8位分頻器

上傳時間： 2013-12-25

上傳用戶：003030

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VHD

VHDl編寫

在FPGA的嵌入式picoblaze設計中使用到的匯編器

四位十進制頻率計設計包含測頻控制器（TESTCTL）

交通燈控制器編碼

空調系統有限狀態自動機編碼

是codic算法實現atan的virilog程序

The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontro

Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci

Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested i

此文件為EDA的8位分頻器