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VHDL-AMS

VHDL-AMS是VHDL的一個分支，它支持模擬、數(shù)字、數(shù)模混合電路系統(tǒng)的建模與仿真。

《VHDL實(shí)用教程》完整版

VHDL入門者值得學(xué)習(xí)!

標(biāo)簽： VHDL 實(shí)用教程

上傳時間： 2014-01-13

上傳用戶：lo25643
VHDl實(shí)用教程(潘_松_王國棟_編著)

VHDL教程

標(biāo)簽： VHDl 實(shí)用教程

上傳時間： 2013-11-11

上傳用戶：2404
vhdl 與數(shù)字電路設(shè)計

VHDL程序講解，配合實(shí)例，適合初學(xué)者，大學(xué)期間可用

標(biāo)簽： vhdl 數(shù)字電路設(shè)計

上傳時間： 2013-11-17

上傳用戶：851197153
The VHDL Cookbook (VHDL編碼書籍)

The VHDL Cookbook是是VHDL編碼書籍。

標(biāo)簽： VHDL Cookbook The 編碼

上傳時間： 2013-11-13

上傳用戶：zhengjian
ZBT SRAM控制器參考設(shè)計,xilinx提供VHDL代碼

ZBT SRAM控制器參考設(shè)計,xilinx提供VHDL代碼 Description: Contains the following files readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf Platform: All Installation/Use: Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.

標(biāo)簽： xilinx SRAM VHDL ZBT

上傳時間： 2013-11-24

上傳用戶：31633073
USB接口控制器參考設(shè)計,xilinx提供VHDL代碼 us

USB接口控制器參考設(shè)計,xilinx提供VHDL代碼 usb xilinx vhdl ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by ; the Free Software Foundation; either version 2 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, ; but WITHOUT ANY WARRANTY; without even the implied warranty of ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ; GNU General Public License for more details. ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software ; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

標(biāo)簽： xilinx VHDL USB us

上傳時間： 2013-10-12

上傳用戶：windgate
ref sdr sdram vhdl代碼

ref-sdr-sdram-vhdl代碼 SDR SDRAM Controller v1.1 readme.txt This readme file for the SDR SDRAM Controller includes information that was not incorporated into the SDR SDRAM Controller White Paper v1.1. The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture. Last updated September, 2002 Copyright ?2002 Altera Corporation. All rights reserved.

標(biāo)簽： sdram vhdl ref sdr

上傳時間： 2013-11-13

上傳用戶：takako_yang
UART 4 UART參考設(shè)計，Xilinx提供VHDL代碼

UART 4 UART參考設(shè)計，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.

標(biāo)簽： UART Xilinx VHDL 參考設(shè)計

上傳時間： 2013-11-07

上傳用戶：jasson5678
各種功能的計數(shù)器實(shí)例（VHDL源代碼）

各種功能的計數(shù)器實(shí)例（VHDL源代碼）:

標(biāo)簽： VHDL 計數(shù)器源代碼

上傳時間： 2013-10-16

上傳用戶：bjgaofei
各種功能的計數(shù)器實(shí)例（VHDL源代碼）

各種功能的計數(shù)器實(shí)例（VHDL源代碼）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;

標(biāo)簽： VHDL 計數(shù)器源代碼

上傳時間： 2014-11-30

上傳用戶：半熟1994