CAM is useful vhdl code to understand its architecture which helps to write any code
標簽： code architecture understand useful
上傳時間： 2017-09-05
上傳用戶：天涯
Workshop vhdl code from Esperan
標簽： Workshop Esperan vhdl code
上傳時間： 2013-12-05
上傳用戶：541657925
Usart model in vhdl code
上傳時間： 2013-12-17
上傳用戶：wxhwjf
Vhdl code for seven segment, in english made by university student
標簽： sseg
上傳時間： 2017-04-23
上傳用戶：friede17
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
Analog-to-Digital Converter，VHDL code
標簽： Analog-to-Digital Converter
上傳時間： 2014-11-30
上傳用戶：cazjing
是關于sigma delta PLL設計的詳細論文，論文中有具體的設計細節，并在附錄中有相應的matlab、vhdl code
上傳時間： 2016-10-24
上傳用戶：maizezhen
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2014-01-02
上傳用戶：二驅蚊器
High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support. For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0 signaling running at hundreds of MHz, the existing design methodology must change.
標簽： technology 2.0 USB designed
上傳時間： 2017-07-05
上傳用戶：zhoujunzhen
這是Originl公司出的8051 VHDL source code.
上傳時間： 2014-01-01
上傳用戶：ljt101007
