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Verilog-A

VERILOG HDL 實(shí)際工控項(xiàng)目源碼

VERILOG HDL 實(shí)際工控項(xiàng)目源碼\r\n開發(fā)工具 altera quartus2

標(biāo)簽： VERILOG HDL 工控項(xiàng)目

上傳時(shí)間： 2013-09-05

上傳用戶：youmo81
Cadence Verilog Language and Simulation

Cadence Verilog Language and Simulation

標(biāo)簽： Simulation Language Cadence Verilog

上傳時(shí)間： 2013-09-06

上傳用戶：yl1140vista
gerber-to-protel is a pdf file

gerber-to-protel is a pdf file ,which is used for convert bmp to pcb.

標(biāo)簽： gerber-to-protel file is

上傳時(shí)間： 2013-09-18

上傳用戶：liuxinyu2016
protel_lib-PIC16 is a protel lib file.

protel_lib-PIC16 is a protel lib file.

標(biāo)簽： protel_lib-PIC protel file lib

上傳時(shí)間： 2013-09-18

上傳用戶：hn891122
Many CAD users dismiss schematic capture as a necessary evil in the process of creating

Many CAD users dismiss schematic capture as a necessary evil in the process of creating\r\nPCB layout but we have always disputed this point of view. With PCB layout now offering\r\nautomation of both component placement and track routing, getting the des

標(biāo)簽： schematic necessary creating dismiss

上傳時(shí)間： 2013-09-25

上傳用戶：baiom
State Machine Coding Styles for Synthesis

本文論述了狀態(tài)機(jī)的verilog編碼風(fēng)格,以及不同編碼風(fēng)格的優(yōu)缺點(diǎn)，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.

標(biāo)簽： Synthesis Machine Coding Styles

上傳時(shí)間： 2013-10-15

上傳用戶：dancnc
VHDL,Verilog,System verilog比較

本文簡(jiǎn)單討論并總結(jié)了VHDL、Verilog，System verilog 這三中語(yǔ)言的各自特點(diǎn)和區(qū)別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.

標(biāo)簽： Verilog verilog System VHDL

上傳時(shí)間： 2013-10-16

上傳用戶：牛布牛
Verilog編碼中的非阻塞性賦值

One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions

標(biāo)簽： Verilog 編碼非阻塞性賦值

上傳時(shí)間： 2013-10-17

上傳用戶：tb_6877751
常用D/A轉(zhuǎn)換器和A/D轉(zhuǎn)換器介紹

　　常用D/A轉(zhuǎn)換器和A/D轉(zhuǎn)換器介紹　　下面我們介紹一下其它常用D/A轉(zhuǎn)換器和 A/D 轉(zhuǎn)換器，便于同學(xué)們?cè)O(shè)計(jì)時(shí)使用。　　1. DAC0808 　　圖 1 所示為權(quán)電流型 D/A 轉(zhuǎn)換器 DAC0808 的電路結(jié)構(gòu)框圖。用 DAC0808 這類器件構(gòu) 成的 D/A轉(zhuǎn)換器，需要外接運(yùn)算放大器和產(chǎn)生基準(zhǔn)電流用的電阻。DAC0808 構(gòu)成的典型應(yīng)用電路如圖2 所示。

標(biāo)簽： 轉(zhuǎn)換器

上傳時(shí)間： 2014-12-23

上傳用戶：zhenyushaw
數(shù)電Verilog相關(guān)課件

數(shù)電Verilog相關(guān)課件

標(biāo)簽： Verilog 數(shù)電

上傳時(shí)間： 2013-10-23

上傳用戶：wangzeng