VERILOG HDL 實際工控項目源碼\r\n開發工具 altera quartus2
上傳時間： 2013-09-05
上傳用戶：youmo81
Cadence Verilog Language and Simulation
標簽： Simulation Language Cadence Verilog
上傳時間： 2013-09-06
上傳用戶：yl1140vista
gerber-to-protel is a pdf file ,which is used for convert bmp to pcb.
標簽： gerber-to-protel file is
上傳時間： 2013-09-18
上傳用戶：liuxinyu2016
protel_lib-PIC16 is a protel lib file.
標簽： protel_lib-PIC protel file lib
上傳時間： 2013-09-18
上傳用戶：hn891122
Many CAD users dismiss schematic capture as a necessary evil in the process of creating\r\nPCB layout but we have always disputed this point of view. With PCB layout now offering\r\nautomation of both component placement and track routing, getting the des
標簽： schematic necessary creating dismiss
上傳時間： 2013-09-25
上傳用戶：baiom
本文論述了狀態機的verilog編碼風格,以及不同編碼風格的優缺點，Steve Golson's 1994 paper, "State Machine Design Techniques for Verilog and VHDL" [1], is agreat paper on state machine design using Verilog, VHDL and Synopsys tools. Steve's paper alsooffers in-depth background concerning the origin of specific state machine types.This paper, "State Machine Coding Styles for Synthesis," details additional insights into statemachine design including coding style approaches and a few additional tricks.
標簽： Synthesis Machine Coding Styles
上傳時間： 2013-10-15
上傳用戶：dancnc
本文簡單討論并總結了VHDL、Verilog，System verilog 這三中語言的各自特點和區別As the number of enhancements to variousHardware Description Languages (HDLs) hasincreased over the past year, so too has the complexityof determining which language is best fora particular design. Many designers and organizationsare contemplating whether they shouldswitch from one HDL to another.
標簽： Verilog verilog System VHDL
上傳時間： 2013-10-16
上傳用戶：牛布牛
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions
上傳時間： 2013-10-17
上傳用戶：tb_6877751
常用D/A轉換器和A/D轉換器介紹 下面我們介紹一下其它常用D/A轉換器和 A/D 轉換器，便于同學們設計時使用。 1. DAC0808 圖 1 所示為權電流型 D/A 轉換器 DAC0808 的電路結構框圖。用 DAC0808 這類器件構 成的 D/A轉換器，需要外接運算放大器和產生基準電流用的電阻。DAC0808 構成的典型應用電路如圖2 所示。
標簽： 轉換器
上傳時間： 2014-12-23
上傳用戶：zhenyushaw
數電Verilog相關課件
上傳時間： 2013-10-23
上傳用戶：wangzeng
