Abstract: Using a wafer-level package (WLP) can reduce the overall size and cost of your solution.However WHEN using a WLP IC, the printed circuit board (PCB) layout can become more complex and, ifnot carefully planned, result in an unreliable design. This article presents some PCB designconsiderations and general recommendations for choosing a 0.4mm- or 0.5mm-pitch WLP for yourapplication.
標簽： Considerations Guidelines and Design
上傳時間： 2013-11-09
上傳用戶：ls530720646
通過以太網遠程配置Nios II 處理器 應用筆記 Firmware in embedded hardware systems is frequently updated over the Ethernet. For embedded systems that comprise a discrete microprocessor and the devices it controls, the firmware is the software image run by the microprocessor. WHEN the embedded system includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as part of the FPGA image—and the software that the Nios II processor runs, in a single remote configuration session.
上傳時間： 2013-11-22
上傳用戶：chaisz
Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit WHEN you use certain implementation switches, andfail to fit WHEN using other switches. This application note attempts to clarify the CPLD softwareimplementation (CPLDFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLD utilization.
上傳時間： 2014-01-11
上傳用戶：a471778
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that WHEN a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時間： 2013-11-24
上傳用戶：18707733937
Finite state machines are widely used in digital circuit designs. Generally, WHEN designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
標簽： Creating Machines Mentor State
上傳時間： 2013-11-02
上傳用戶：xauthu
Calculation of the Differential Impedance of Tracks on FR4 substrates There is a discrepancy between calculated and measured values of impedance for differential transmission lineson FR4. This is especially noticeable in the case of surface microstrip configurations. The anomaly is shown tobe due to the nature of the substrate material. This needs to be considered as a layered structure of epoxy resinand glass fibre. Calculations, using Boundary Element field methods, show that the distribution of the electricfield within this layered structure determines the apparent dielectric constant and therefore affects theimpedance. Thus FR4 cannot be considered to be uniform dielectric WHEN calculating differential impedance.
上傳時間： 2013-10-18
上傳用戶：masochism
Abstract: Many modern industrial, medical, and commercial applications require temperature measurements in the extended temperature rangewith accuracies of ±0.3°C or better, performed with reasonable cost and often with low power consumption. This article explains how platinumresistance temperature detectors (PRTDs) can perform measurements over wide temperature ranges of -200°C to +850°C, with absolute accuracyand repeatability better than ±0.3°C, WHEN used with modern processors capable of resolving nonlinear mathematical equation quickly and costeffectively. This article is the second installment of a series on PRTDs. For the first installment, please read application note 4875, "High-Accuracy Temperature Measurements Call for Platinum Resistance Temperature Detectors (PRTDs) and Precision Delta-Sigma ADCs."
上傳時間： 2013-11-06
上傳用戶：WMC_geophy
Abstract: This application note explains how to design an intelligent lighting controller that senses and measures the ambient lightlevel with an ambient light sensor (ALS). Equipped with a real-time clock (RTC), the controller also knows WHEN to turn lighting on oroff at specified times. The system presented in this document can be used to control all luminaires that are mains-supply operated.Controller software is also provided in hex format.
上傳時間： 2013-11-18
上傳用戶：AbuGe
Modern electronic systems solve so many difficult problems that they often seem like magic. Nonetheless, these systems all have thesame basic limitation: they need a source of electrical power! Most of the time this is a straightforward challenge for the electronicdesigner, because there are many power-delivery solutions. Yet sometimes a device has no direct power source, and running wiresor replacing batteries is impractical. Even WHEN long-life batteries are usable, they eventually need to be replaced, which requires aservice call.
標簽： 能量收集
上傳時間： 2015-01-03
上傳用戶：zukfu
Abstract: How can an interface change a happy face to a sad face? Engineers have happy faces WHEN an interface works properly.Sad faces indicate failure somewhere. Because interfaces between microprocessors and ICs are simple—even easy—they are oftenignored until interface failure causes sad faces all around. In this article, we discuss a common SPI error that can be almostimpossible to find in a large system. Links to interface tutorial information are provided for complete information. Noise as a systemissue and ICs to minimize its effects are also described.
上傳時間： 2013-11-18
上傳用戶：zgz317
