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This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A WIDE variety of references are listed. Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use.
上傳時間： 2014-12-31
上傳用戶：PresidentHuang
Nios II軟件構建工具入門 The Nios® II Software Build Tools (SBT) allows you to construct a WIDE variety of complex embedded software systems using a command-line interface. From this interface, you can execute Software Built Tools command utilities, and use scripts other tools) to combine the command utilities in many useful ways. This chapter introduces you to project creation with the SBT at the command line This chapter includes the following sections: ■ “Advantages of Command-Line Software Development” ■ “Outline of the Nios II SBT Command-Line Interface” ■ “Getting Started in the SBT Command Line” ■ “Software Build Tools Scripting Basics” on page 3–8
上傳時間： 2013-11-15
上傳用戶：nanxia
Express Mode uses an 8-bit WIDE bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
標簽： Spartan-XL Express XAPP FPGA
上傳時間： 2015-01-02
上傳用戶：nanxia
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. Most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a WIDE range of assemblytypes and complexities.
上傳時間： 2013-11-20
上傳用戶：pzw421125
We would like to welcome you as a user of the Allegro CX, a rugged, handheld fi eld PC for data collection. Developed with the input of data collection professionals worldWIDE, the Allegro CX is adaptable and versatile for use in a WIDE variety of data collection environments. The Allegro CX continues to utilize our ergonomic, lightweight design that is standard in our line of Allegro Field PCs. This design makes your Allegro easy to use for extended periods while moving to and from data collection sites in the fi eld.
上傳時間： 2015-01-02
上傳用戶：zhangyi99104144
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a WIDE variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標簽： Transceiver Virtex Wizar GTP
上傳時間： 2013-10-20
上傳用戶：dave520l
Abstract: Many modern industrial, medical, and commercial applications require temperature measurements in the extended temperature rangewith accuracies of ±0.3°C or better, performed with reasonable cost and often with low power consumption. This article explains how platinumresistance temperature detectors (PRTDs) can perform measurements over WIDE temperature ranges of -200°C to +850°C, with absolute accuracyand repeatability better than ±0.3°C, when used with modern processors capable of resolving nonlinear mathematical equation quickly and costeffectively. This article is the second installment of a series on PRTDs. For the first installment, please read application note 4875, "High-Accuracy Temperature Measurements Call for Platinum Resistance Temperature Detectors (PRTDs) and Precision Delta-Sigma ADCs."
上傳時間： 2013-11-06
上傳用戶：WMC_geophy
There are many manufacturers of dot matrix LCD modules. However, most of these displaysare similar. They all have on-board controllers and drivers capable of displaying alpha numericsand a WIDE variety of other symbols (including Japanese "Katakana" characters). The internaloperation of LCD controller devices is determined by signals sent from a central processing unit(in this case, a CoolRunner-II CPLD).
標簽： CoolRunner-II XAPP 904 LCD
上傳時間： 2013-12-17
上傳用戶：haiya2000
此為本人期末的課程設計VC設計:瀏覽器程序設計。注：本源碼用Word文檔存放。 簡介內容:隨著互聯網在世界范圍的廣泛應用，WWW（World WIDE Web,萬維網）也日益成為互聯網上信息交流不可缺少的工具。它是一種以HTTP（HyperText Tranfer Protocol,超文本傳輸協議）為基礎，使用HTML（HypeText Markup Language,超文本標記語言）編寫的有若干Web網頁構筑而成的世界。 本課程設計要求設計類似于微軟的IE瀏覽器，具備一個瀏覽器的基本功能，可以完成網上沖浪的任務。 設計 Visual C++為我們提供了一個ChtmlView類，有了它。可以很方便地設計瀏覽器。
上傳時間： 2015-03-29
上傳用戶：亞亞娟娟123
The I2C Memory Model is a generic Proteus VSM model designed to model the timing and functionality of I2C memory devices from a WIDE range of manufacturers.
標簽： model functionality designed Proteus
上傳時間： 2015-04-25
上傳用戶：Divine
