基于FPGA設(shè)計(jì)的sdram讀寫測(cè)試實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號(hào),容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數(shù)據(jù)寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號(hào)都是時(shí)鐘信號(hào)。FPGA型號(hào)Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram WRITE enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,WRITE data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst WRITE finish
標(biāo)簽： fpga sdram verilog quartus
上傳時(shí)間： 2021-12-18
上傳用戶：
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 WRITE Leveling.......................................................................................................................................................314.7.1 DRAM setting for WRITE leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 WRITE Leveling Mode Exit .........................................................................................................................34
標(biāo)簽： DDR4
上傳時(shí)間： 2022-01-09
上傳用戶：
Extensively rewritten to present the C++11 language, standard library, and key design techniques as an integrated whole, Stroustrup thoroughly addresses changes that make C++11 feel like a whole new language, offering definitive guidance for leveraging its improvements in performance, reliability, and clarity. C++ programmers around the world recognize Bjarne Stoustrup as the go-to expert for the absolutely authoritative and exceptionally useful information they need to WRITE outstanding C++ programs. Now, as C++11 compilers arrive and development organizations migrate to the new standard, they know exactly where to turn once more: Stoustrup's C++ Programming Language, Fourth Edition.Bjarne Stroustrup是C++的設(shè)計(jì)師和最早的實(shí)現(xiàn)者，也是《C++程序設(shè)計(jì)語(yǔ)言》、《帶標(biāo)注的C++參考手冊(cè)》和《C++語(yǔ)言的設(shè)計(jì)與演化》的作者。他從丹麥Aarhus大學(xué)和英國(guó)牛津大學(xué)畢業(yè)，現(xiàn)在是AT&T大規(guī)模程序設(shè)計(jì)研究部的負(fù)責(zé)人，AT&T特別成員，AT&T貝爾實(shí)驗(yàn)室特別成員，以及ACM特別成員。Stroustrup的研究興趣包括分布式系統(tǒng)、操作系統(tǒng)、模擬、設(shè)計(jì)和程序設(shè)計(jì)。他也是Addison·Wesley的C++In-Depth系列書籍的編輯。
標(biāo)簽： C++
上傳時(shí)間： 2022-02-01
上傳用戶：
verilog實(shí)現(xiàn)I2C通信的slave模塊源碼狀態(tài)機(jī)設(shè)位計(jì)可做I2C接口的仿真模型//`timescale 1ns/1psmodule I2C_slv (input [6:0] slv_id,input RESET,input scl_i, //I2C clkinput sda_i, //I2C data ininput [7:0] I2C_RDDATA,////////////////////////output reg sda_o, //I2C data outoutput reg reg_w, //reg WRITE enable pulse (1T of scl_i)output reg [7:0] I2C_ADDR,output reg [7:0] I2C_DATA); parameter ST_ADDR = 4'd0; parameter ST_ACK = 4'd1; parameter ST_WDATA1 = 4'd2; parameter ST_WACK1 = 4'd3; parameter ST_WDATA2 = 4'd4; parameter ST_WACK2 = 4'd5; parameter ST_WDATA3 = 4'd6; parameter ST_WACK3 = 4'd7; parameter ST_RDATA1 = 4'd8; parameter ST_RACK1 = 4'd9; parameter ST_IDLE = 4'd15;//---------------------------------------------------------------------------// Signal Declaration//--------------------------------------------------------------------------- reg i2c_start_n, i2c_stop_n; //wire RESET_scl; wire i2c_stp_n, i2c_RESET; reg [3:0] i2c_cs, i2c_ns; reg [3:0] cnt_bit; reg [7:0] d_vec; reg i2c_rd, i2c_ack; reg [7:0] I2C_RDDATA_latch;
標(biāo)簽： verilog i2c 通信 slave
上傳時(shí)間： 2022-02-03
上傳用戶：
因此，您想編寫一個(gè)內(nèi)核模塊。您知道C，您已經(jīng)編寫了一些可以作為進(jìn)程運(yùn)行的常規(guī)程序，現(xiàn)在您想知道真正的動(dòng)作在哪里，一個(gè)通配指針可以擦掉文件系統(tǒng)，核心轉(zhuǎn)儲(chǔ)意味著重新啟動(dòng)。內(nèi)核模塊到底是什么？模塊是可以根據(jù)需要加載和卸載的代碼段。它們擴(kuò)展了內(nèi)核的功能，而無需重新引導(dǎo)系統(tǒng)。例如。模塊驅(qū)動(dòng)程序的一種類型是設(shè)備驅(qū)動(dòng)程序，它允許內(nèi)核訪問沒有模塊的系統(tǒng)硬件，我們將不得不構(gòu)建單片內(nèi)核并將新功能直接添加到內(nèi)核映像中，除了具有更大的內(nèi)核之外，這還具有缺點(diǎn)每次我們想要新功能時(shí)都要求我們重建并重新啟動(dòng)內(nèi)核的過程So, you want to WRITE a kernel module. You know C, you, ve written a few normal programs to run as processes, and now you want to get to where the real action is, to where a single wild pointer can wipe out your file system and a core dump means a reboot.What exactly is a kernel module? Modules are pieces of code that can be loaded and unloaded into th upon demand. They extend the functionality of the kernel without the need to reboot the system. For example.one type of module is the device driver, which allows the kernel to access hardware connected to the syste without modules, we would have to build monolithic kernels and add new functionality directly into the em ernel image, Besides having larger kernels
標(biāo)簽： linux
上傳時(shí)間： 2022-03-30
上傳用戶：
意法半導(dǎo)體STM8系列參考手冊(cè)Program memory: 8 Kbyte Flash memory; dataretention 20 years at 55 °C after 100 cycles? RAM: 1 Kbyte? Data memory: 128 bytes true data EEPROM;endurance up to 100 k WRITE/erase cycles
標(biāo)簽： stm8
上傳時(shí)間： 2022-04-27
上傳用戶：zhaiyawei
BLE heart rate profile document.this is can help you how to WRITE a profile.
標(biāo)簽： ble
上傳時(shí)間： 2022-04-30
上傳用戶：
3.DDR布線細(xì)節(jié)i.MX6DDR的布線，可以將所有信號(hào)分成3組：數(shù)據(jù)線組、地址線組和控制線組，每組各自設(shè)置自己的布線規(guī)則，但同時(shí)也要考慮組與組之間的規(guī)則。3.1數(shù)據(jù)線的交換在DDR3的布線中，可以根據(jù)實(shí)際情況交換數(shù)據(jù)線的線序，但必須保證是以字節(jié)為單位（數(shù)據(jù)0~7間是允許交換線序，跨字節(jié)是不允許的），這樣可以簡(jiǎn)化設(shè)計(jì)。■布線盡量簡(jiǎn)短，減少過孔數(shù)量。■布線時(shí)避免改變走線參考層面。■數(shù)據(jù)線線序，推薦DO、D8、D16、D24、D32、D40、D48、D56不要改變，其它的數(shù)據(jù)線可以在字節(jié)內(nèi)自由調(diào)換（see the“WRITE Leveling"sectioninJESD79-3E■DQS和DQM不能調(diào)換，必須在相應(yīng)通道。3.2DDR3（64bits）T型拓?fù)浣榻B當(dāng)設(shè)計(jì)采用T型拓?fù)浣Y(jié)構(gòu)，請(qǐng)確認(rèn)以下信息。■布線規(guī)則見上文表2。■終端電阻可以省略。■布線長(zhǎng)度的控制。DDR數(shù)量限制在4片以下。
標(biāo)簽： ddr3
上傳時(shí)間： 2022-07-05
上傳用戶：
在.cshrc中添加以下設(shè)定：setenV NOVAS_HOME <Verdi_install_dir>set path=（$path $NOVAS_HOME/bin）setenV NOVAS_LICENSE_FILE <full_path>/<license_file>Orsetenv NOVAS_LICENSE_FILE 5219@hostname（環(huán)境變量NOVAS_LICENSE_FILE優(yōu)先級(jí)高于LM_LICENSE_FILE）內(nèi)容：>預(yù)編譯設(shè)計(jì)前設(shè)置匹配信息·將庫(kù)名字匹配到相應(yīng)物理地址·格式[Library]logical name=physical locationpack=../1ibrary/pack用戶參數(shù)設(shè)置（set via Tools>Preferences）調(diào)用其它novas.rc（可選項(xiàng)）指定搜索路徑…>使用環(huán)境變量NOVAS_RCsetenv NOVAS_RC <path>/novas.rc>命令行中直接調(diào)用-rcFile <filename>搜索順序1.-rcFile <filename>命令行參數(shù)（read/WRITE pointer）2.NOVAS_RC環(huán)境變量（read/WRITE pointer）3../novas.rc4.$HOME/novas.rc5.<Verdi install>/etc/novas.rc
標(biāo)簽： verdi
上傳時(shí)間： 2022-07-20
上傳用戶：
VIP專區(qū)-嵌入式/單片機(jī)編程源碼精選合集系列（57）資源包含以下內(nèi)容：1. 12864漢字液晶顯示驅(qū)動(dòng)程序.2. LCD液晶程序.3. Scan image DSP process Sca n image DSP process Sca n image DSP process Sca n image DSP process.4. PIC16F946 底層驅(qū)動(dòng).5. PIC16F946 底層驅(qū)動(dòng).6. cpld簡(jiǎn)單的教程.7. 針對(duì)嵌入式micro window系統(tǒng).8. PPC下的文本編輯器源代碼.9. PDIUSBD12USB固件編程與驅(qū)動(dòng)開發(fā)周立功D12Win98驅(qū)動(dòng)源碼.10. C/C++嵌入式系統(tǒng)編程.11. 此文檔為adi公司arm7tdmi內(nèi)核的aduc70XX系列各模塊的源代碼.12. 這是用CH375芯片做的u盤轉(zhuǎn)存的例子.13. 這是一個(gè)關(guān)于一個(gè)無線通訊芯片的無線的link的程序.14. msp430的iic通訊子程序.15. PADS2005中文教程.16. protel的常用器件庫(kù) protel的常用器件庫(kù) protel的常用器件庫(kù).17. cnstl970一款經(jīng)典一款經(jīng)典 cnstl970一款經(jīng)典.18. 1602a經(jīng)典資料 1602a經(jīng)典資料.19. 一個(gè)計(jì)時(shí)程序.20. LED程序.21. windriver公司的vxworks系統(tǒng)是專業(yè)的嵌入式實(shí)時(shí)操作系統(tǒng).22. 提供FAT16文件系統(tǒng)在嵌入式操作系統(tǒng)U_COS中的方案.23. 傅立葉變換程序 傅立葉變換程序.24. 請(qǐng)先刪除編譯后的debug/release.25. 液晶資料 液晶資料 液晶資料.26. 液晶資料 液晶資料 液晶資料 液晶資料 液晶資料 液晶資料 液晶資料 液晶資料.27. 液晶資料 液晶資料 液晶資料 液晶資料 液晶資料 液晶資料 液晶資料 液晶資料.28. 液晶資料 液晶資料 液晶資料 液晶資料 液晶資料.29. PHILIPS LPC76X D/A 實(shí)例程序.30. 為SYT240160CZK液晶顯示的驅(qū)動(dòng).31. 該原碼主要介紹如何在DSP上實(shí)現(xiàn)視頻輸入與輸出的代碼,基于DSP6000系列的..32. LCD顯示測(cè)試程序.33. 基于雙NIOS II 的IP無線收發(fā)機(jī) 2006年嵌入式電子大賽獲獎(jiǎng)作品.34. 2006altera大賽－基于軟核Nios的寬譜正弦信號(hào)發(fā)生器設(shè)計(jì)：摘要：本設(shè)計(jì)運(yùn)用了基于 Nios II 嵌入式處理器的 SOPC 技術(shù)。系統(tǒng)以 ALTERA公司的 Cyclone 系列 FPGA.35. Zigbee document about system structure.36. Samsung KS0719 graphical LCD (SPI) This driver allows to draw points and to WRITE characters on thi.37. C51 API 例子源碼.38. Api_for_usb_products 源碼．.39. avr mega8 pwm 試驗(yàn)帶 Proteus 仿真.40. Alterla官方版ep1c20 FPGA NOISII開發(fā)板原理圖.
上傳時(shí)間： 2013-04-15
上傳用戶：eeworm
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