Use A/D channel scan mode in dspic programming
標簽： programming channel dspic scan
上傳時間： 2016-02-03
上傳用戶：bibirnovis
Designing Storage Area Networks - A Practical Reference For Implementing Fibre Channel And Ip Sans, Second Edition
標簽： Implementing Designing Practical Reference
上傳時間： 2016-02-08
上傳用戶：410805624
A 6 Channel PPM PIC code for 12F629 and 12F675，There are four examples here and they are work well for RC receiver.
標簽： Channel 12F629 12F675 code
上傳時間： 2013-12-23
上傳用戶：lindor
// 移頻選頻原理 //Fvco=[(P*B)+A]*Frefin/R //P=32 //loop filter 100k----prescribe //R=12.8M/100K=128---Parameter1 //Fvco=頻點*2+170280 -1400 //B=Fvco/32-----------Parameter2 //A=Fvco-32*B
標簽： 100 prescribe Frefin filter
上傳時間： 2013-12-26
上傳用戶：dancnc
Rayleigh 信道仿真模型 參考"Autoregressive modeling for fading channel simulation", IEEE Transaction on Wireless Communications, July 2005.
標簽： Autoregressive Transaction simulation Rayleigh
上傳時間： 2016-03-15
上傳用戶：zwei41
Mahafza B.R, Elsherbeni A.Z. - MATLAB Simulations for Radar Systems Design - 2004 對于雷達系統設計師來說這是一本難得的寶典
標簽： A.Z. Simulations Elsherbeni Mahafza
上傳時間： 2016-03-20
上傳用戶：pinksun9
上以A R M 芯片為例,詳細分析了在發生中斷時如何實現中斷現場的保護以及一 般嵌入式操作系統的多任務切換過程
上傳時間： 2013-12-13
上傳用戶：BOBOniu
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN generation) 2) Modulator (RRC filter) 3) Demodulator (Matched Filter, RAKE receiver) 4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
標簽： simulation baseband channel packet
上傳時間： 2014-12-20
上傳用戶：ukuk
A paper on WiMax Simulation. The simulation include transmitter, receiver and channel model. AMC and MIMO are used.
標簽： transmitter Simulation simulation and
上傳時間： 2013-12-01
上傳用戶：金宜
This example provides a description of how to use a DMA channel to transfer a word data buffer from memory (Flash) to memory (RAM). The dedicated DMA channel is configured to transfer once a time a 32 word data buffer stored as constant in the Flash memory to another buffer in the RAM memory. The received data are stored in the DST_Buffer. The DMA channel transfer complete interrupt is enabled to generate an interrupt at the end of the buffer transfer. As soon as the transfer is completed an interrupt is generated and in the DMA channel interrupt routine the transfer complete interrupt pending bit is cleared. The data counter is stored before and after the transfer to show that all data has been transfered. TransferStatus gives the data transfer status where it is PASSED if transmitted and received data are the same otherwise it is FAILED
標簽： description provides transfer example
上傳時間： 2016-04-24
上傳用戶：ecooo
