This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate.
The simulation is written for static channel and AWGN noise. The packet include:
1) Packet Builder (Viterbi Encoding, Interleaver, PN generation)
2) Modulator (RRC filter)
3) Demodulator (Matched Filter, RAKE receiver)
4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
This example provides a description of how to use a DMA channel to transfer a
word data buffer from memory (Flash) to memory (RAM).
The dedicated DMA channel is configured to transfer once a time a 32 word data buffer
stored as constant in the Flash memory to another buffer in the RAM memory.
The received data are stored in the DST_Buffer.
The DMA channel transfer complete interrupt is enabled to generate an interrupt at
the end of the buffer transfer. As soon as the transfer is completed an interrupt is
generated and in the DMA channel interrupt routine the transfer complete interrupt
pending bit is cleared.
The data counter is stored before and after the transfer to show that all data has been
transfered.
TransferStatus gives the data transfer status where it is PASSED if transmitted and
received data are the same otherwise it is FAILED
