常用D/A轉換器和A/D轉換器介紹 下面我們介紹一下其它常用D/A轉換器和 A/D 轉換器，便于同學們設計時使用。 1. DAC0808 圖 1 所示為權電流型 D/A 轉換器 DAC0808 的電路結構框圖。用 DAC0808 這類器件構 成的 D/A轉換器，需要外接運算放大器和產生基準電流用的電阻。DAC0808 構成的典型應用電路如圖2 所示。
標簽： 轉換器
上傳時間： 2014-12-23
上傳用戶：zhenyushaw
isoad系列產品實現傳感器和主機之間的信號安全隔離和高精度數字采集與傳輸，廣泛應用于rs-232/485總線工業自動化控制系統，4-20ma / 0-10v信號測量、監視和控制，小信號的測量以及工業現場信號隔離及長線傳輸等遠程監控場合。通過軟件的配置，可接入多種傳感器類型，包括電流輸出型、電壓輸出型、以及熱電偶等等。 產品內部包括電源隔離，信號隔離、線性化，a/d轉換和rs-485串行通信等模塊。每個串口最多可接256只iso ad系列模塊，通訊方式采用ascii 碼字符通訊協議或modbus rtu通訊協議，其指令集兼容于adam模塊，波特率可由用戶設置，能與其他廠家的控制模塊掛在同一rs-485總線上，便于主機編程。 isoad系列產品是基于單片機的智能監測和控制系統，所有用戶設定的校準值，地址，波特率，數據格式，校驗和狀態等配置信息都儲存在非易失性存儲器eeprom里。 isoad系列產品按工業標準設計、制造，信號輸入 / 輸出之間隔離，可承受3000vdc隔離電壓，抗干擾能力強，可靠性高。工作溫度范圍- 45℃～+80℃。
上傳時間： 2013-11-23
上傳用戶：comer1123
本次在線座談主要介紹TI的高精度Delta-Sigma A/D轉換器的原理及其應用，Delta-Sigma A/D轉換器在稱重儀器中，大量采用比例測量方法。
標簽： Delta-Sigma 高精度 轉換器
上傳時間： 2013-10-17
上傳用戶：zhqzal1014
The STM32F10xxx microcontroller family embeds up to three advanced 12-bit ADCs (depending on the device) with a conversion time down to 1 μs. A self-calibration feature is provided to enhance ADC accuracy versus environmental condition changes.
上傳時間： 2014-12-23
上傳用戶：eastimage
Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full scale. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full Scale Error): The difference between theoutput voltage (or current) with full scale input code and theideal voltage (or current) that should exist with a full scale inputcode.Gain Temperature Coefficient (Full Scale TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full scale).Can be expressed as a percentage of full scale or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full scale voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.
標簽： Converters Defini DAC
上傳時間： 2013-10-30
上傳用戶：stvnash
ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE JITTER is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
上傳時間： 2013-11-12
上傳用戶：pans0ul
cv181l-a-20
標簽： Specification_V 181 1.0 L-A
上傳時間： 2013-11-14
上傳用戶：daijun20803
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2013-10-15
上傳用戶：busterman
2012TI杯陜西賽題H題,2012TI杯陜西賽題-A微弱信號檢測裝置.
上傳時間： 2013-12-17
上傳用戶：362279997
2011全國大賽A題開關電源模塊并聯供電系統
上傳時間： 2013-11-10
上傳用戶：冇尾飛鉈
