-
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
標簽：
XAPP
740
AXI
互聯
上傳時間：
2013-11-23
上傳用戶：shen_dafa
-
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標簽：
Efficient
Verilog
Digital
Coding
上傳時間：
2013-11-23
上傳用戶：我干你啊
-
One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.
標簽：
Synplicity
Machine
Verilog
Design
上傳時間：
2013-10-20
上傳用戶：蒼山觀海
-
Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.
標簽：
Creating
Machines
Mentor
State
上傳時間：
2013-11-02
上傳用戶：xauthu
-
ZBT SRAM控制器參考設計,xilinx提供VHDL代碼
Description:
Contains the following files
readme.txt appnote_zbtp.vhd appnote_zbtf.vhd appnote_zbt.ucf
Platform:
All
Installation/Use:
Use 'unzip' on the .zip file and 'gunzip' followed by 'tar -xvf' on the .tar.gz file.
標簽：
xilinx
SRAM
VHDL
ZBT
上傳時間：
2013-10-25
上傳用戶：peterli123456
-
ref-sdr-sdram-vhdl代碼
SDR SDRAM Controller v1.1 readme.txt
This readme file for the SDR SDRAM Controller includes information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.
The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture.
Last updated September, 2002
Copyright ?2002 Altera Corporation. All rights reserved.
標簽：
sdram
vhdl
ref
sdr
上傳時間：
2013-10-23
上傳用戶：半熟1994
-
Silicon Motion, Inc. has made best efforts to ensure that the information contained in this document is accurate andreliable. However, the information is subject to change without notice. No responsibility is assumed by SiliconMotion, Inc. for the use of this information, nor for infringements of patents or other rights of third parties.Copyright NoticeCopyright 2002, Silicon Motion, Inc. All rights reserved. No part of this publication may be reproduced, photocopied,or transmitted in any form, without the prior written consent of Silicon Motion, Inc. Silicon Motion, Inc. reserves theright to make changes to the product specification without reservation and without notice to our users
標簽：
GUIDELINES
LAYOUT
320
PCB
上傳時間：
2013-10-10
上傳用戶：manga135
-
PCB設計問題集錦
問：PCB圖中各種字符往往容易疊加在一起，或者相距很近，當板子布得很密時，情況更加嚴重。當我用Verify Design進行檢查時，會產生錯誤，但這種錯誤可以忽略。往往這種錯誤很多，有幾百個，將其他更重要的錯誤淹沒了，如何使Verify Design會略掉這種錯誤，或者在眾多的錯誤中快速找到重要的錯誤。 答：可以在顏色顯示中將文字去掉,不顯示后再檢查;并記錄錯誤數目。但一定要檢查是否真正屬于不需要的文字。
問： What’s mean of below warning:(6230,8330 L1) Latium Rule not checked: COMPONENT U26 component rule.答：這是有關制造方面的一個檢查，您沒有相關設定，所以可以不檢查。
問： 怎樣導出jop文件？答：應該是JOB文件吧？低版本的powerPCB與PADS使用JOB文件。現在只能輸出ASC文件，方法如下STEP：FILE/EXPORT/選擇一個asc名稱/選擇Select ALL/在Format下選擇合適的版本/在Unit下選Current比較好/點擊OK/完成然后在低版本的powerPCB與PADS產品中Import保存的ASC文件，再保存為JOB文件。
問： 怎樣導入reu文件？答：在ECO與Design 工具盒中都可以進行，分別打開ECO與Design 工具盒，點擊右邊第2個圖標就可以。 問： 為什么我在pad stacks中再設一個via:1(如附件）和默認的standardvi(如附件）在布線時V選擇1，怎么布線時按add via不能添加進去這是怎么回事，因為有時要使用兩種不同的過孔。答：PowerPCB中有多個VIA時需要在Design Rule下根據信號分別設置VIA的使用條件，如電源類只能用Standard VIA等等，這樣操作時就比較方便。詳細設置方法在PowerPCB軟件通中有介紹。
問：為什么我把On-line DRC設置為prevent..移動元時就會彈出(圖2),而你們教程中也是這樣設置怎么不會呢?答：首先這不是錯誤,出現的原因是在數據中沒有BOARD OUTLINE.您可以設置一個,但是不使用它作為CAM輸出數據.
問：我用ctrl+c復制線時怎設置原點進行復制，ctrl+v粘帖時總是以最下面一點和最左邊那一點為原點 答： 復制布線時與上面的MOVE MODE設置沒有任何關系,需要在右鍵菜單中選擇,這在PowerPCB軟件通教程中有專門介紹.
問：用(圖4)進行修改線時拉起時怎總是往左邊拉起(圖5)，不知有什么辦法可以輕易想拉起左就左，右就右。答： 具體條件不明,請檢查一下您的DESIGN GRID,是否太大了.
問： 好不容易拉起右邊但是用(圖6)修改線怎么改怎么下面都會有一條不能和在一起，而你教程里都會好好的(圖8)答：這可能還是與您的GRID 設置有關,不過沒有問題,您可以將不需要的那段線刪除.最重要的是需要找到布線的感覺,每個軟件都不相同,所以需要多練習。
問： 尊敬的老師:您好！這個圖已經畫好了，但我只對（如圖1）一種的完全間距進行檢查，怎么錯誤就那么多，不知怎么改進。請老師指點。這個圖在附件中請老師幫看一下，如果還有什么問題請指出來，本人在改進。謝！！！！！答：請注意您的DRC SETUP窗口下的設置是錯誤的,現在選中的SAME NET是對相同NET進行檢查,應該選擇NET TO ALL.而不是SAME NET有關各項參數的含義請仔細閱讀第5部教程.
問： U101元件已建好，但元件框的拐角處不知是否正確，請幫忙CHECK 答：元件框等可以通過修改編輯來完成。問： U102和U103元件沒建完全，在自動建元件參數中有幾個不明白：如：SOIC--》silk screen欄下spacing from pin與outdent from first pin對應U102和U103元件應寫什么數值，還有這兩個元件SILK怎么自動設置，以及SILK內有個圓圈怎么才能畫得與該元件參數一致。
答：Spacing from pin指從PIN到SILK的Y方向的距離,outdent from first pin是第一PIN與SILK端點間的距離.請根據元件資料自己計算。
標簽：
PCB
設計問題
集錦
上傳時間：
2014-01-03
上傳用戶：Divine
-
This document provides practical, common guidelines for incorporating PCI Express interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are intended
for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI
Express devices located on the same baseboard (chip-to-chip routing) and interconnects between
a PCI Express device located “down” on the baseboard and a device located “up” on an add-in
card attached through a connector.
This document is intended to cover all major components of the physical interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the interconnect for all layouts and implementations.
Therefore, designers should consider modeling and simulation of the interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main sections. The first section provides an overview of
general topology and interconnect guidelines. The second section concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
標簽：
pci
PCB
設計規范
上傳時間：
2014-01-24
上傳用戶：s363994250
-
這個軟件需要你的本機操作的。其他機器是算不出來的！
就是說 一臺電腦只有一個注冊碼對應！
這里有個辦法：
MULTISIM2001安裝方法：
一：運行SETUP.EXE安裝。在安裝時，要重新啟動計算機一次。
二：啟動后在“開始>程序”中找到STARTUP項，運行后，繼續進行安裝，安裝過程中，第一次要求輸入“CODE"碼時，
輸入“PP-0411-48015-7464-32084"輸入后，會提示"VALID SERIAL NUMBER FOR MULTISIM 2001 POWER-PRO."
按確定，又會出現一個“feature code”框，輸入“FC-6424-04180-0044-13881”后，
在彈出的對話框中選擇“取消”，一路確定即可完成安裝。
三：1.運行VERILOG目錄內的SETUP安裝
2.運行FPGA目錄內的SETUP安裝
3.將CRACK目錄內的LICMGR.DLL拷貝到WINDOWS系統的SYSTEM 目錄內
4.并將VERILOG安裝目錄內的同名文件刪除
5.將SILOS.LIC文件拷到VERILOG安裝目錄內覆蓋原文件，并作如下編輯：
6.將“COMPUTER_NAME”替換為你的機器名
7.將“D:\MULTISIM\VERILOG\PATH_TO_SIMUCAD.EXE”替換為你的
實際安裝路徑。如此你便可以使用VERILOG了。
四：安裝之后，運行MULTISIM2001,會要求輸入“RELEASE CODE",不用著急，
記下“SERIAL NUMBER"和“SIGNATURE NUMBER",
使用CRACK目錄內的注冊器“MULTISIM KEYGEN.EXE"
將剛才記下的兩個號碼分別填入后，
即可得到"RELEASE CODE", 以后就可以正常使用了。
五：接下來運行 database update目錄中的幾個文件，
進行數據庫合并即可。祝你成功！！
六：啟動MULTISIM2001時候的注冊碼
1：
PP-0411-48015-7464-32084
2：
37506-86380
3:的三個空格
1975 2711 4842
里面包含了：Multisim2001漢化破解版、Multisim.V10.0.1.漢化破解版圖解
解壓密碼：www.pp51.com
標簽：
Multisim
2001
漢化破解版
免費下載
上傳時間：
2013-11-16
上傳用戶：天空說我在
