This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish reliable data and information, but the author and the publisher cannot assume responsibility for the validity of all materials or for the consequences of their use.
上傳時(shí)間： 2014-12-31
上傳用戶：PresidentHuang
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is Port ( clk : in std_logic; resetn : in std_logic; dout : out std_logic_vector(7 downto 0); lcd_en : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic); end counter;
標(biāo)簽： lcd 計(jì)數(shù)顯示 程序
上傳時(shí)間： 2013-10-30
上傳用戶：wqxstar
C++在幾乎所有的計(jì)算環(huán)境中都非常普及，而且可以用于幾乎所有的應(yīng)用程序。C++從C中繼承了過程化編程的高效性，并集成了面向?qū)ο缶幊痰墓δ堋++在其標(biāo)準(zhǔn)庫(kù)中提供了大量的功能。有許多商業(yè)C++庫(kù)支持?jǐn)?shù)量眾多的操作系統(tǒng)環(huán)境和專業(yè)應(yīng)用程序。但因?yàn)樗膬?nèi)容太多了，所以掌握C++并不十分容易。本書詳述了C++語(yǔ)言的各個(gè)方面，包括數(shù)據(jù)類型、程序控制、函數(shù)、指針、調(diào)試、類、重載、繼承、多態(tài)性、模板、異常和輸入輸出等內(nèi)容。每一章都以前述內(nèi)容為基礎(chǔ)，每個(gè)關(guān)鍵點(diǎn)都用具體的示例進(jìn)行詳細(xì)的講解。本書基本不需要讀者具備任何C++知識(shí)，書中包含了理解C++的所有必要知識(shí)，讀者可以從頭開始編寫自己的C++程序。本書也適合于具備另一種語(yǔ)言編程經(jīng)驗(yàn)但希望全面掌握C++語(yǔ)言的讀者。 I created all the files under Microsoft Windows so lines are terminated by CR/LF. In addition to this "ReadMe" file you will find three zip archives in the primary archive, so you need to unzip each of these to get at the code. 為PDG格式,這有pdg閱讀器下載|pdg文件閱讀器下載
標(biāo)簽： 源代碼
上傳時(shí)間： 2013-11-18
上傳用戶：gaoqinwu
資料說明介紹 PCB Translator_CAMCAD轉(zhuǎn)換器3.95版本，里面含CAMCAD_3.9.5a_crack文件，可以對(duì)軟件進(jìn)行破解 （需要安裝PCB Translator后才能進(jìn)行破解） 針對(duì)PCB設(shè)計(jì)文件的RSI轉(zhuǎn)換器能夠轉(zhuǎn)換PCB設(shè)計(jì)和生產(chǎn)所需要的所有信息。它們包括：庫(kù)，布置位置，插入屬性信息，網(wǎng)表，走線，文字和銅箔，以及其它相關(guān)的項(xiàng)目。不需要執(zhí)行"導(dǎo)入Gerber"和"交叉參考"就可以完成所有這些工作。事實(shí)上，根本不需要定義參考，因?yàn)檐浖梢詮脑嘉募袷街刑崛〕鯟AD數(shù)據(jù)，并把它直接輸出到新的文件格式中。只需要注意CAD系統(tǒng)本身的限制就可以了。 CAMCAD PCB 轉(zhuǎn)換器 CAMCAD PCB 轉(zhuǎn)換器是一個(gè)功能完善的PCB CAD 轉(zhuǎn)換器，圖形用戶界面也很淺顯易懂。CAMCAD PCB 轉(zhuǎn)換器支持大多數(shù)流行的CAD格式，比如Cadence Allegro, Orcad, Mentor and Accel EDA,也支持工業(yè)標(biāo)準(zhǔn)格式，比如GenCAM, GenCAD, and IPC-D-356.CAMCAD PCB 轉(zhuǎn)換器允許導(dǎo)入CAD文件到CAMCAD圖形用戶環(huán)境中，校驗(yàn)數(shù)據(jù)，修改數(shù)據(jù)，然后可以把數(shù)據(jù)導(dǎo)出為任意格式的文件。這些特性意味著用戶可以完全控制所有的事情，比如層的轉(zhuǎn)換，也能解決CAD格式之間不兼容的問題。 一個(gè)案例,如果要轉(zhuǎn)換Cadence Allegro文件到PADS,所有必須的設(shè)計(jì)信息都會(huì)包含在新的文件中。不過，Cadence Allegro允許板子上的銅箔重疊，PADS卻不允許。Allegro 文件可以正常導(dǎo)入到CAMCAD。如果要立即把這個(gè)文件導(dǎo)出到PADS，程序會(huì)有錯(cuò)誤提示。這時(shí)，可以使用CAMCAD的數(shù)據(jù)處理特性來(lái)改變有問題的銅箔，解決問題后再導(dǎo)出到PADS。 下面的矩陣表格，列出了CAMCAD PCB 轉(zhuǎn)換器所支持的當(dāng)前PCB的轉(zhuǎn)換組合。Import Modules 一列中列出了可以被導(dǎo)入（讀取）的所有ECAD文件格式。Export Modules一行中列出了可以被導(dǎo)出（寫）的文件格式。在這個(gè)矩陣中的任意輸入和輸出模塊組合轉(zhuǎn)換都是可行的。當(dāng)然，沒有任何ECAD到ECAD的轉(zhuǎn)換器是絕對(duì)完美的。由于ECAD layout系統(tǒng)有自己獨(dú)特的特性，而這些可能不能直接轉(zhuǎn)換到另一個(gè)有自己獨(dú)特特性的ECAD系統(tǒng)中。 CAMCAD PCB 轉(zhuǎn)換器支持的組合 建議配置：Windows 2000 或者 XP Professional，800 MHZ 處理器，512MB RAM 17"顯示器，1024×768分辨率 Copyright 2004 Router Solutions Incorporated RSI Reserves the right to make changes to its specifications and products without prior notice. CAMCAD is a registered trademark of Router Solutions Incorporated. All rights reserved. RSI recognizes other brand and product names as trademarks or registered trademarks of their respective holders.
標(biāo)簽： Translator_CAMCAD PCB 轉(zhuǎn)換器
上傳時(shí)間： 2014-07-31
上傳用戶：Shaikh
資料說明介紹 PCB Translator_CAMCAD轉(zhuǎn)換器3.95版本，里面含CAMCAD_3.9.5a_crack文件，可以對(duì)軟件進(jìn)行破解 （需要安裝PCB Translator后才能進(jìn)行破解） 針對(duì)PCB設(shè)計(jì)文件的RSI轉(zhuǎn)換器能夠轉(zhuǎn)換PCB設(shè)計(jì)和生產(chǎn)所需要的所有信息。它們包括：庫(kù)，布置位置，插入屬性信息，網(wǎng)表，走線，文字和銅箔，以及其它相關(guān)的項(xiàng)目。不需要執(zhí)行"導(dǎo)入Gerber"和"交叉參考"就可以完成所有這些工作。事實(shí)上，根本不需要定義參考，因?yàn)檐浖梢詮脑嘉募袷街刑崛〕鯟AD數(shù)據(jù)，并把它直接輸出到新的文件格式中。只需要注意CAD系統(tǒng)本身的限制就可以了。 CAMCAD PCB 轉(zhuǎn)換器 CAMCAD PCB 轉(zhuǎn)換器是一個(gè)功能完善的PCB CAD 轉(zhuǎn)換器，圖形用戶界面也很淺顯易懂。CAMCAD PCB 轉(zhuǎn)換器支持大多數(shù)流行的CAD格式，比如Cadence Allegro, Orcad, Mentor and Accel EDA,也支持工業(yè)標(biāo)準(zhǔn)格式，比如GenCAM, GenCAD, and IPC-D-356.CAMCAD PCB 轉(zhuǎn)換器允許導(dǎo)入CAD文件到CAMCAD圖形用戶環(huán)境中，校驗(yàn)數(shù)據(jù)，修改數(shù)據(jù)，然后可以把數(shù)據(jù)導(dǎo)出為任意格式的文件。這些特性意味著用戶可以完全控制所有的事情，比如層的轉(zhuǎn)換，也能解決CAD格式之間不兼容的問題。 一個(gè)案例,如果要轉(zhuǎn)換Cadence Allegro文件到PADS,所有必須的設(shè)計(jì)信息都會(huì)包含在新的文件中。不過，Cadence Allegro允許板子上的銅箔重疊，PADS卻不允許。Allegro 文件可以正常導(dǎo)入到CAMCAD。如果要立即把這個(gè)文件導(dǎo)出到PADS，程序會(huì)有錯(cuò)誤提示。這時(shí)，可以使用CAMCAD的數(shù)據(jù)處理特性來(lái)改變有問題的銅箔，解決問題后再導(dǎo)出到PADS。 下面的矩陣表格，列出了CAMCAD PCB 轉(zhuǎn)換器所支持的當(dāng)前PCB的轉(zhuǎn)換組合。Import Modules 一列中列出了可以被導(dǎo)入（讀取）的所有ECAD文件格式。Export Modules一行中列出了可以被導(dǎo)出（寫）的文件格式。在這個(gè)矩陣中的任意輸入和輸出模塊組合轉(zhuǎn)換都是可行的。當(dāng)然，沒有任何ECAD到ECAD的轉(zhuǎn)換器是絕對(duì)完美的。由于ECAD layout系統(tǒng)有自己獨(dú)特的特性，而這些可能不能直接轉(zhuǎn)換到另一個(gè)有自己獨(dú)特特性的ECAD系統(tǒng)中。 CAMCAD PCB 轉(zhuǎn)換器支持的組合 建議配置：Windows 2000 或者 XP Professional，800 MHZ 處理器，512MB RAM 17"顯示器，1024×768分辨率 Copyright 2004 Router Solutions Incorporated RSI Reserves the right to make changes to its specifications and products without prior notice. CAMCAD is a registered trademark of Router Solutions Incorporated. All rights reserved. RSI recognizes other brand and product names as trademarks or registered trademarks of their respective holders.
標(biāo)簽： Translator_CAMCAD PCB 轉(zhuǎn)換器
上傳時(shí)間： 2014-12-31
上傳用戶：wvbxj
Xilinx UltraScale™ 架構(gòu)針對(duì)要求最嚴(yán)苛的應(yīng)用，提供了前所未有的ASIC級(jí)的系統(tǒng)級(jí)集成和容量。 UltraScale架構(gòu)是業(yè)界首次在All Programmable架構(gòu)中應(yīng)用最先進(jìn)的ASIC架構(gòu)優(yōu)化。該架構(gòu)能從20nm平面FET結(jié)構(gòu)擴(kuò)展至16nm鰭式FET晶體管技術(shù)甚至更高的技術(shù)，同 時(shí)還能從單芯片擴(kuò)展到3D IC。借助Xilinx Vivado®設(shè)計(jì)套件的分析型協(xié)同優(yōu)化，UltraScale架構(gòu)可以提供海量數(shù)據(jù)的路由功能，同時(shí)還能智能地解決先進(jìn)工藝節(jié)點(diǎn)上的頭號(hào)系統(tǒng)性能瓶頸。 這種協(xié)同設(shè)計(jì)可以在不降低性能的前提下達(dá)到實(shí)現(xiàn)超過90%的利用率。 UltraScale架構(gòu)的突破包括： • 幾乎可以在晶片的任何位置戰(zhàn)略性地布置類似于ASIC的系統(tǒng)時(shí)鐘，從而將時(shí)鐘歪斜降低達(dá)50% • 系統(tǒng)架構(gòu)中有大量并行總線，無(wú)需再使用會(huì)造成時(shí)延的流水線，從而可提高系統(tǒng)速度和容量 • 甚至在要求資源利用率達(dá)到90%及以上的系統(tǒng)中，也能消除潛在的時(shí)序收斂問題和互連瓶頸 • 可憑借3D IC集成能力構(gòu)建更大型器件，并在工藝技術(shù)方面領(lǐng)先當(dāng)前行業(yè)標(biāo)準(zhǔn)整整一代 • 能在更低的系統(tǒng)功耗預(yù)算范圍內(nèi)顯著提高系統(tǒng)性能，包括多Gb串行收發(fā)器、I/O以及存儲(chǔ)器帶寬 • 顯著增強(qiáng)DSP與包處理性能 賽靈思UltraScale架構(gòu)為超大容量解決方案設(shè)計(jì)人員開啟了一個(gè)全新的領(lǐng)域。
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-12-23
上傳用戶：小儒尼尼奧
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
面向Eclips的Nios II軟件構(gòu)建工具手冊(cè) The Nios® II Software Build Tools (SBT) for Eclipse™ is a set of plugins based on the Eclipse™ framework and the Eclipse C/C++ development toolkit (CDT) plugins. The Nios II SBT for Eclipse provides a consistent development platform that works for all Nios II embedded processor systems. You can accomplish all Nios II software development tasks within Eclipse, including creating, editing, building, running, debugging, and profiling programs.
上傳時(shí)間： 2013-11-02
上傳用戶：瓦力瓦力hong
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
標(biāo)簽： Efficient Verilog Digital Coding
上傳時(shí)間： 2013-11-23
上傳用戶：我干你啊
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