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analysis-Synthesis

  • Debussy 50

    Debussy軟件 Debussy是NOVAS Software, Inc(思源科技)發(fā)展的HDL Debug & Analysis tool,這套軟體主要不是用來(lái)跑模擬或看波形

    標(biāo)簽: Debussy 50

    上傳時(shí)間: 2013-07-08

    上傳用戶:fywz

  • 算法FPGA實(shí)現(xiàn)的直接數(shù)字頻率合成器

    高精度的信號(hào)源是各種測(cè)試和實(shí)驗(yàn)過(guò)程中不可缺少的工具,在通信、雷達(dá)、測(cè)量、控制、教學(xué)等領(lǐng)域應(yīng)用十分廣泛。傳統(tǒng)的頻率合成方法設(shè)計(jì)的信號(hào)源在功能、精度、成本等方面均存在缺陷和不足,不能滿足電子技術(shù)的發(fā)展要求,直接數(shù)字合成(Direct Digital Synthesis)DDS技術(shù)可以提供高性能、高頻高精度的信號(hào)源,方便地獲得分辨率高且相位連續(xù)的信號(hào),基于FPGA的DDS技術(shù)提供了升級(jí)方便并且成本低廉的解決方案。    本文對(duì)DDS的基本原理和輸出頻譜特性進(jìn)行理論分析,總結(jié)出雜散分布規(guī)律。同時(shí)以DDS的頻譜分析為基礎(chǔ),給出了幾種改善雜散的方法。本文結(jié)合相關(guān)文獻(xiàn)資料采用傅立葉變換的方法對(duì)相位截?cái)鄷r(shí)DDS雜散信號(hào)的頻譜特性進(jìn)行了研究,得到了雜散分布的規(guī)律性結(jié)論,并應(yīng)用在程序設(shè)計(jì)程中;DDS技術(shù)的實(shí)現(xiàn)依賴于高速、高性能的數(shù)字器件,本文將FPGA器件和DDS技術(shù)相結(jié)合,確定了FPGA器件的整體設(shè)計(jì)方案,詳細(xì)說(shuō)明了各個(gè)模塊的功能和設(shè)計(jì)方法,并對(duì)其關(guān)鍵部分進(jìn)行了優(yōu)化設(shè)計(jì),從而實(shí)現(xiàn)了波形發(fā)生器數(shù)字電路部分的功能。軟件部分采用模塊設(shè)計(jì)方法,十分方便調(diào)試。為了得到滿足設(shè)計(jì)要求的模擬波形,本文還設(shè)計(jì)了幅度調(diào)節(jié)、D/A轉(zhuǎn)換和低通濾波等外圍硬件電路。    實(shí)驗(yàn)結(jié)果表明,本文設(shè)計(jì)的基于DDS技術(shù)的多波形信號(hào)源基本能夠滿足普通學(xué)生實(shí)驗(yàn)室的要求。

    標(biāo)簽: FPGA 算法 數(shù)字頻率合成器

    上傳時(shí)間: 2013-06-11

    上傳用戶:woshiayin

  • C++寫(xiě)的DTMF算法

    ·詳細(xì)說(shuō)明:C++寫(xiě)的DTMF算法,內(nèi)含一個(gè)pcm數(shù)據(jù)文件,讀入文件并分析按鍵-c writes the DTMF algorithm, contains a pcm data file, the read-in document and the analysis pressed key。文件列表:   DTMF   ....\DTMF.cpp   ....\DTMF.

    標(biāo)簽: DTMF 算法

    上傳時(shí)間: 2013-04-24

    上傳用戶:Miyuki

  • 數(shù)字圖像處理與分析(劉定生老師)

    ·詳細(xì)說(shuō)明:數(shù)字圖像處理與分析-劉定生老師, 非常好的講述數(shù)字圖像處理的課件,包括所有基本的圖像處理知識(shí),Image processing ang analysis by Teacher LiuDingsheng, very good for you to study the knowledge of image processing

    標(biāo)簽: 數(shù)字圖像處理

    上傳時(shí)間: 2013-04-24

    上傳用戶:visit8888

  • an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysi

    1.an fpga implementation of the image space reconstruction algorithm for hyperspectral imaging analysis\r\n2. fpga implemention of a median filter\r\n3. fpga implementation of digital filters\r\n4.hardware acceleration of edge detection algorithm on fpgas

    標(biāo)簽: implementation reconstruction hyperspectral algorithm

    上傳時(shí)間: 2013-08-07

    上傳用戶:ytulpx

  • Guide to HDL Coding Styles for Synthesis

    這篇文章討論了不同HDL代碼的編寫(xiě)方式,對(duì)綜合結(jié)果的影響。閱讀本文對(duì)深入了解綜合工具和提高HDL的編寫(xiě)水平有不少幫助,原文時(shí)針對(duì)Synopsys的綜合軟件論述的,但對(duì)所有綜合軟件,都有普遍的借鑒意義  

    標(biāo)簽: Synthesis Coding Styles Guide

    上傳時(shí)間: 2014-12-23

    上傳用戶:huql11633

  • RF至數(shù)字接收器的信號(hào)鏈噪聲分析

      Designers of signal receiver systems often need to performcascaded chain analysis of system performancefrom the antenna all the way to the ADC. Noise is a criticalparameter in the chain analysis because it limits theoverall sensitivity of the receiver. An application’s noiserequirement has a signifi cant infl uence on the systemtopology, since the choice of topology strives to optimizethe overall signal-to-noise ratio, dynamic range andseveral other parameters. One problem in noise calculationsis translating between the various units used by thecomponents in the chain: namely the RF, IF/baseband,and digital (ADC) sections of the circuit.

    標(biāo)簽: 數(shù)字接收器 信號(hào)鏈 噪聲分析

    上傳時(shí)間: 2014-12-05

    上傳用戶:cylnpy

  • 高速數(shù)字系統(tǒng)設(shè)計(jì)下載pdf

    高速數(shù)字系統(tǒng)設(shè)計(jì)下載pdf:High-Speed Digital SystemDesign—A Handbook ofInterconnect Theory and DesignPracticesStephen H. HallGarrett W. HallJames A. McCallA Wiley-Interscience Publication JOHN WILEY & SONS, INC.New York • Chichester • Weinheim • Brisbane • Singapore • TorontoCopyright © 2000 by John Wiley & Sons, Inc.speeddigital systems at the platform level. The book walks the reader through everyrequired concept, from basic transmission line theory to digital timing analysis, high-speedmeasurement techniques, as well as many other topics. In doing so, a unique balancebetween theory and practical applications is achieved that will allow the reader not only tounderstand the nature of the problem, but also provide practical guidance to the solution.The level of theoretical understanding is such that the reader will be equipped to see beyondthe immediate practical application and solve problems not contained within these pages.Much of the information in this book has not been needed in past digital designs but isabsolutely necessary today. Most of the information covered here is not covered in standardcollege curricula, at least not in its focus on digital design, which is arguably one of the mostsignificant industries in electrical engineering.The focus of this book is on the design of robust high-volume, high-speed digital productssuch as computer systems, with particular attention paid to computer busses. However, thetheory presented is applicable to any high-speed digital system. All of the techniquescovered in this book have been applied in industry to actual digital products that have beensuccessfully produced and sold in high volume.Practicing engineers and graduate and undergraduate students who have completed basicelectromagnetic or microwave design classes are equipped to fully comprehend the theorypresented in this book. At a practical level, however, basic circuit theory is all thebackground required to apply the formulas in this book.

    標(biāo)簽: 高速數(shù)字 系統(tǒng)設(shè)計(jì)

    上傳時(shí)間: 2013-10-26

    上傳用戶:縹緲

  • 模擬電路設(shè)計(jì)CMOS Analog Circuit Desi

    I.1 IntroductionI.2 Analog Integrated Circuit DesignI.3 Technology OverviewI.4 NotationI.5 Analog Circuit Analysis Techniques

    標(biāo)簽: Circuit Analog CMOS Desi

    上傳時(shí)間: 2013-10-29

    上傳用戶:jokey075

  • Design Safe Verilog State Machine(Synplicity)

      One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.

    標(biāo)簽: Synplicity Machine Verilog Design

    上傳時(shí)間: 2013-10-23

    上傳用戶:司令部正軍級(jí)

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