波形發生器，帶TESTBENCH， 多平臺 -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn
標簽： 波形發生器
上傳時間： 2014-01-20
上傳用戶：familiarsmile
Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline architecture to compress and decompress images. The real filter calculation over 4 · 4 window blocks is done using a tree of carry save adders to ensure the high speed processing required for many applications. The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis reveals that the proposed architecture, implemented using current VLSI technologies, can process a video stream in real time.
標簽： applications processing Wavelets widely
上傳時間： 2014-01-22
上傳用戶：hongmo
1)Learn more about the capabilities in Quartus: 2)Learn to use different design entry techniques 2)Design entry methods available within Quartus Text editor,Block diagram/schematic file editor, Quartus interface with design entry/synthesis tools from Exemplar, Synopsys, Synplicity and Viewlogic
標簽： Learn capabilities techniques different
上傳時間： 2014-01-18
上傳用戶：yxgi5
關于FPGA流水線設計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.
標簽： investigates implementing pipelines circuits
上傳時間： 2015-07-26
上傳用戶：CHINA526
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis to the public transportation systems engineering to design ,Java,software engineering
標簽： transportation engineering documents including
上傳時間： 2015-08-15
上傳用戶：lixinxiang
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis to the public transportation systems engineering to design ,Java,software
標簽： transportation engineering documents including
上傳時間： 2013-12-26
上傳用戶：Zxcvbnm
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis to the public transportation systems engineering to design ,Java
標簽： transportation engineering documents including
上傳時間： 2015-08-15
上傳用戶：caixiaoxu26
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis to the public transportation systems engineering to
標簽： transportation engineering documents including
上傳時間： 2015-08-15
上傳用戶：時代電子小智
This was the public transportation inquiry system software engineering design documents, including the demand analysis, the outline design, the contact surface design and so on a series of designs documents, made the comprehensive analysis
標簽： transportation engineering documents including
上傳時間： 2014-01-07
上傳用戶：saharawalker
一個非常好的時間序列工具箱，詳細使用說明見P. M. T. Broersen, Automatic Spectral Analysis with Time Series Models, IEEE Transactions on Instrumentation and Measurement, Vol. 51, No. 2, April 2002, pp. 211-216.
上傳時間： 2014-01-14
上傳用戶：古谷仁美
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