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analysis-Synthesis

  • DDR SDRAM控制器的VHDL源代碼

    DDR SDRAM控制器的VHDL源代碼,含詳細設計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.

    標簽: SDRAM VHDL DDR 控制器

    上傳時間: 2014-11-01

    上傳用戶:l254587896

  • 一個自然語言處理的Java開源工具包。LingPipe目前已有很豐富的功能

    一個自然語言處理的Java開源工具包。LingPipe目前已有很豐富的功能,包括主題分類(Top Classification)、命名實體識別(Named Entity Recognition)、詞性標注(Part-of Speech Tagging)、句題檢測(Sentence Detection)、查詢拼寫檢查(Query Spell Checking)、興趣短語檢測(Interseting Phrase Detection)、聚類(Clustering)、字符語言建模(Character Language Modeling)、醫學文獻下載/解析/索引(MEDLINE Download, Parsing and Indexing)、數據庫文本挖掘(Database Text Mining)、中文分詞(Chinese Word Segmentation)、情感分析(Sentiment Analysis)、語言辨別(Language Identification)等API。

    標簽: LingPipe Java 自然語言處理 開源

    上傳時間: 2013-12-04

    上傳用戶:15071087253

  • 97 law to enhance the classic procedure Ridge wavelet extraction Modulus maximum for the wavelet

    97 law to enhance the classic procedure Ridge wavelet extraction Modulus maximum for the wavelet edge detection Small spectral analysis method mallat classic procedure

    標簽: wavelet extraction the procedure

    上傳時間: 2014-01-09

    上傳用戶:xg262122

  • 編譯原理課程設計

    編譯原理課程設計,包括詞法,語 義分析,功能全面!-the class design about principle of complier.it contains analysis of word ,gram and mine about language .

    標簽: 編譯原理

    上傳時間: 2014-01-04

    上傳用戶:zhuyibin

  • Design of Integrated Circuits for Optical Communications deals with the design of high-speed integra

    Design of Integrated Circuits for Optical Communications deals with the design of high-speed integrated circuits for optical communication systems. Written for both students and practicing engineers, the book systematically takes the reader from basic concepts to advanced topics, establishing both rigor and intuition. The text emphasizes analysis and design in modern VLSI technologies, particularly CMOS, and presents numerous broadband circuit techniques. Leading researcher Behzad Razavi is also the author of Design of Analog CMOS Integrated Circuits.

    標簽: Communications Integrated high-speed Circuits

    上傳時間: 2013-12-21

    上傳用戶:zhouchang199

  • ECE345, Visual-to-Audio Electronic Travel Aid Code for TM320C54x (v2a.asm) download This project

    ECE345, Visual-to-Audio Electronic Travel Aid Code for TM320C54x (v2a.asm) download This project involves the design and implementation of a audio synthesis device that converts moving images into audio signals. The system is built on a TM320C54x DSP with interface to an IMAQ camera module via the serial port on a PC. Brief description: A LabVIEW VI acquires an image from the IMAQ camera module. It quantizes the image into a 5x5, 3-bit image, and sends the data to the TM320C54x DSP via a serial port. The TM320C54x DSP constructs a 64-tap FIR by combining a series of 64-tap head related transfer functions (HRTF) according to the incoming data, and then filters an input audio signal with this FIR filter, in effect creating a correspondence between the filtered signal and the original image.

    標簽: Visual-to-Audio Electronic download project

    上傳時間: 2017-02-01

    上傳用戶:笨小孩

  • 正則表達式的分析解釋控件

    正則表達式的分析解釋控件,適用于delphi各版本-is a regular expression analysis explained Control, applicable to all versions of delphi [引自此網絡]

    標簽: 控件 表達式

    上傳時間: 2017-02-02

    上傳用戶:

  • 8051單片機源碼verilog版本 包括rtl

    8051單片機源碼verilog版本 包括rtl, testbench, synthesis

    標簽: verilog 8051 rtl 單片機

    上傳時間: 2014-01-14

    上傳用戶:yuanyuan123

  • 1. Learn the basic constructs of VHDL 2. Learn the modeling structure of VHDL 3. Understand the de

    1. Learn the basic constructs of VHDL 2. Learn the modeling structure of VHDL 3. Understand the design environments – Simulation – Synthesis

    標簽: the Learn VHDL Understand

    上傳時間: 2017-02-18

    上傳用戶:love_stanford

  • Ictclas分詞系統

    Ictclas分詞系統,文詞法分析是中文信息處理的基礎與關鍵。中國科學院計算技術研究所在多年研究工作積累的基礎上,研制出了漢語詞法分析系統ICTCLAS(Institute of Computing Technology, Chinese Lexical Analysis System)

    標簽: Ictclas

    上傳時間: 2017-02-18

    上傳用戶:569342831

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