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assign

Insert table of contents: Create some pages, assign labels to them and insert a table of conten

Insert table of contents: Create some pages, assign labels to them and insert a table of contents at the beginning of the document

標簽： table contents Insert Create

上傳時間： 2016-04-20

上傳用戶：zuozuo1215
FPGA Verilog,雙向端口的研究,比較全,由assign和ALWAYS模塊組成,測試可用

FPGA Verilog,雙向端口的研究,比較全,由assign和ALWAYS模塊組成,測試可用

標簽： Verilog assign ALWAYS FPGA

上傳時間： 2016-04-27

上傳用戶：daoxiang126
可視界面監獄管理系統添加更改刪除獄警囚犯增加減少囚犯服刑年限顯示獄警工作年限增加減少獄警工資 assign獄警囚犯到不同囚室

可視界面監獄管理系統添加更改刪除獄警囚犯增加減少囚犯服刑年限顯示獄警工作年限增加減少獄警工資 assign獄警囚犯到不同囚室，等

標簽： assign 減可視刪除

上傳時間： 2013-12-26

上傳用戶：alan-ee
同一基類型的兩分辨類型的賦值相容問題,各個源描述的編譯順序是:logic.vhd,assign.vhd

同一基類型的兩分辨類型的賦值相容問題,各個源描述的編譯順序是:logic.vhd,assign.vhd

標簽： vhd assign logic 分辨

上傳時間： 2014-12-05

上傳用戶：ghostparker
The combinatorial core of the OVSF code assignment problem that arises in UMTS is to assign some no

The combinatorial core of the OVSF code assignment problem that arises in UMTS is to assign some nodes of a complete binary tree of height h (the code tree) to n simultaneous connections, such that no two assigned nodes (codes) are on the same root-to-leaf path. Each connection requires a code on a specified level. The code can change over time as long as it is still on the same level. We consider the one-step code assignment problem: Given an assignment, move the minimum number of codes to serve a new request. Minn and Siu proposed the so-called DCAalgorithm to solve the problem optimally. We show that DCA does not always return an optimal solution, and that the problem is NP-hard. We give an exact nO(h)-time algorithm, and a polynomial time greedy algorithm that achieves approximation ratio Θ(h). Finally, we consider the online code assignment problem for which we derive several results

標簽： combinatorial assignment problem arises

上傳時間： 2014-01-19

上傳用戶：BIBI
Your application should never assign a seat that has already been assigned. When the economy sectio

Your application should never assign a seat that has already been assigned. When the economy section is full, your application should ask the person if it is acceptable to be placed in the first-class section (and vice versa). If yes, make the appropriate seat assignment.

標簽： application assigned already economy

上傳時間： 2014-10-25

上傳用戶：zhichenglu
FPGA Verilog

FPGA Verilog,雙向端口的研究,比較全,由assign和ALWAYS模塊組成,測試可用

標簽： Verilog FPGA

上傳時間： 2013-08-22

上傳用戶：longlong12345678
Hyperlynx仿真應用:阻抗匹配

Hyperlynx仿真應用:阻抗匹配.下面以一個電路設計為例，簡單介紹一下PCB仿真軟件在設計中的使用。下面是一個DSP硬件電路部分元件位置關系(原理圖和PCB使用PROTEL99SE設計)，其中DRAM作為DSP的擴展Memory(64位寬度，低8bit還經過3245接到FLASH和其它芯片)，DRAM時鐘頻率133M。因為頻率較高，設計過程中我們需要考慮DRAM的數據、地址和控制線是否需加串阻。下面，我們以數據線D0仿真為例看是否需要加串阻。模型建立首先需要在元件公司網站下載各器件IBIS模型。然后打開Hyperlynx,新建LineSim File(線路仿真—主要用于PCB前仿真驗證)新建好的線路仿真文件里可以看到一些虛線勾出的傳輸線、芯片腳、始端串阻和上下拉終端匹配電阻等。下面，我們開始導入主芯片DSP的數據線D0腳模型。左鍵點芯片管腳處的標志，出現未知管腳，然后再按下圖的紅線所示線路選取芯片IBIS模型中的對應管腳。 3http://bbs.elecfans.com/ 電子技術論壇 http://www.elecfans.com 電子發燒友點OK后退到“assign Models”界面。選管腳為“Output”類型。這樣，一樣管腳的配置就完成了。同樣將DRAM的數據線對應管腳和3245的對應管腳IBIS模型加上(DSP輸出，3245高阻，DRAM輸入)。下面我們開始建立傳輸線模型。左鍵點DSP芯片腳相連的傳輸線，增添傳輸線，然后右鍵編輯屬性。因為我們使用四層板，在表層走線，所以要選用“Microstrip”，然后點“Value”進行屬性編輯。這里，我們要編輯一些PCB的屬性，布線長度、寬度和層間距等，屬性編輯界面如下：再將其它傳輸線也添加上。這就是沒有加阻抗匹配的仿真模型(PCB最遠直線間距1.4inch，對線長為1.7inch)。現在模型就建立好了。仿真及分析下面我們就要為各點加示波器探頭了，按照下圖紅線所示路徑為各測試點增加探頭：為發現更多的信息，我們使用眼圖觀察。因為時鐘是133M，數據單沿采樣，數據翻轉最高頻率為66.7M，對應位寬為7.58ns。所以設置參數如下：之后按照芯片手冊制作眼圖模板。因為我們最關心的是接收端(DRAM)信號，所以模板也按照DRAM芯片HY57V283220手冊的輸入需求設計。芯片手冊中要求輸入高電平VIH高于2.0V，輸入低電平VIL低于0.8V。DRAM芯片的一個NOTE里指出，芯片可以承受最高5.6V，最低-2.0V信號(不長于3ns)：按下邊紅線路徑配置眼圖模板：低8位數據線沒有串阻可以滿足設計要求，而其他的56位都是一對一，經過仿真沒有串阻也能通過。于是數據線不加串阻可以滿足設計要求，但有一點需注意，就是寫數據時因為存在回沖，DRAM接收高電平在位中間會回沖到2V。因此會導致電平判決裕量較小，抗干擾能力差一些，如果調試過程中發現寫RAM會出錯，還需要改版加串阻。

標簽： Hyperlynx 仿真阻抗匹配

上傳時間： 2013-11-05

上傳用戶：dudu121
6小時學會labview

6小時學會labview, labview Six Hour Course – Instructor Notes This zip file contains material designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are: Instructor Notes.doc – this document. labviewIntroduction-SixHour.ppt – a PowerPoint presentation containing screenshots and notes on the topics covered by the course. Convert C to F (Ex1).vi – Exercise 1 solution VI. Convert C to F (Ex2).vi – Exercise 2 solution subVI. Thermometer-DAQ (Ex2).vi – Exercise 2 solution VI. Temperature Monitor (Ex3).vi – Exercise 3 solution VI. Thermometer (Ex4).vi – Exercise 4 solution subVI. Convert C to F (Ex4).vi – Exercise 4 solution subVI. Temperature Logger (Ex4).vi – Exercise 4 solution VI. Multiplot Graph (Ex5).vi – Exercise 5 solution VI. Square Root (Ex6).vi – Exercise 6 solution VI. State Machine 1 (Ex7).vi – Exercise 7 solution VI. The slides can be presented in two three hour labs, or six one hour lectures. Depending on the time and resources available in class, you can choose whether to assign the exercises as homework or to be done in class. If you decide to assign the exercises in class, it is best to assign them in order with the presentation. This way the students can create VI’s while the relevant information is still fresh. The notes associated with the exercise slide should be sufficient to guide the students to a solution. The solution files included are one possible solution, but by no means the only solution.

標簽： labview

上傳時間： 2013-10-13

上傳用戶：zjwangyichao
Foundation入門—仿真

Explain how to open the Waveform Viewer for Verification ? State how to insert nodes into the Waveform Viewer ? Tell how to assign Stimulus with the Stimulator Selector

標簽： Foundation 仿真

上傳時間： 2013-11-05

上傳用戶：gps6888

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assign

Insert table of contents: Create some pages, assign labels to them and insert a table of conten

FPGA Verilog,雙向端口的研究,比較全,由assign和ALWAYS模塊組成,測試可用

可視界面監獄管理系統添加更改刪除獄警囚犯增加減少囚犯服刑年限顯示獄警工作年限增加減少獄警工資 assign獄警囚犯到不同囚室

同一基類型的兩分辨類型的賦值相容問題,各個源描述的編譯順序是:logic.vhd,assign.vhd

The combinatorial core of the OVSF code assignment problem that arises in UMTS is to assign some no

Your application should never assign a seat that has already been assigned. When the economy sectio

FPGA Verilog

Hyperlynx仿真應用:阻抗匹配

6小時學會labview

Foundation入門—仿真