<strike id="gqymi"></strike>
<button id="gqymi"></button> 基于FPGA設(shè)計(jì)的vga顯示測試實(shí)驗(yàn)Verilog邏輯源碼Quartus工程文件+文檔說明，F(xiàn)PGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r = video_r[7:3]; //discard low bit dataassign vga_out_g = video_g[7:2]; //discard low bit dataassign vga_out_b = video_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule
標(biāo)簽： fpga vga顯示 verilog quartus
上傳時(shí)間： 2021-12-19
上傳用戶：kingwide
FPGA片內(nèi)FIFO讀寫測試Verilog邏輯源碼Quartus工程文件+文檔說明，使用 FPGA 內(nèi)部的 FIFO 以及程序?qū)υ?FIFO 的數(shù)據(jù)讀寫操作。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz時(shí)鐘 input rst_n //復(fù)位信號，低電平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO寫數(shù)據(jù)wire wr_en; //FIFO寫使能wire rd_en; //FIFO讀使能wire[15:0] r_data; //FIFO讀數(shù)據(jù)wire full; //FIFO滿信號 wire empty; //FIFO空信號 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///產(chǎn)生FIFO寫入的數(shù)據(jù)always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空， 開始寫FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO滿 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///產(chǎn)生FIFO讀的數(shù)據(jù)always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO滿, 開始讀FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)
標(biāo)簽： fpga fifo verilog quartus
上傳時(shí)間： 2021-12-19
上傳用戶：20125101110
This Getting Started Guide is written for Maxwell beginners and experienced users who would like to quickly re familiarize themselves with the capabilities of MaxwelL.This guide leads you step-by-step through solving and analyzing the results of a rotational actuator magnetostatic problem with motion By following the steps in this guide, you will learn how to perform the following tasks Modify a models design parameters y assign variables to a model's design parameters.Specify solution settings for a design Validate a designs setupRun a maxwell simulation v Plot the magnetic flux density vecto v Include motion in the simulation本《入門指南》是為希望快速重新熟悉MaxwelL功能的Maxwell初學(xué)者和有經(jīng)驗(yàn)的用戶編寫的。本指南將引導(dǎo)您逐步解決和分析旋轉(zhuǎn)致動器靜運(yùn)動問題的結(jié)果。按照本指南中的步驟，您將學(xué)習(xí)如何執(zhí)行以下任務(wù)。修改模型設(shè)計(jì)參數(shù)y將變量分配給模型的設(shè)計(jì)參數(shù)。指定設(shè)計(jì)的解決方案設(shè)置驗(yàn)證設(shè)計(jì)設(shè)置運(yùn)行maxwell模擬v繪制磁通密度vecto v在模擬中包含運(yùn)動
上傳時(shí)間： 2022-03-10
上傳用戶：
【例3.1]4位全加器module adder 4（cout，sum i na，i nb，cin）；output[3：0]sum output cout；input[3：0]i na，i nb；input cin；assign（cout，suml=i na +i nb+ci n；endmodule【例3.2]4位計(jì)數(shù)器module count 4（out，reset，clk）；output[3：0]out；input reset，cl k；regl 3：01 out；always@posedge clk）
標(biāo)簽： verilog
上傳時(shí)間： 2022-06-16
上傳用戶：canderile
蟲蟲下載站版權(quán)所有 京ICP備2021023401號-1
<li id="u444w"></li>