Ideal for large low power (nanoWatt) and connectivity applications that benefit from the availability of four serial ports: double synchronous serial ports (I² C™ and SPI™ ) and double asynchronous (LIN capable) serial ports. Large amounts of RAM memory for buffering and FLASH program memory make it ideal for instrumentation panels, TCP/IP enabled embedded applications as well as metering and industrial control and monitoring applications. While operating up to 40 MHz, it is also backward software and hardware compatible with the PIC18F8720.
標(biāo)簽： connectivity applications availabilit nanoWatt
上傳時(shí)間： 2016-02-04
上傳用戶：CHINA526
本人收集的ajax一些資料，打印版。 Ajax這個(gè)概念的最早提出者Jesse James Garrett認(rèn)為： Ajax是asynchronous JavaScript and XML的縮寫。 Ajax并不是一門新的語言或技術(shù),它實(shí)際上是幾項(xiàng)技術(shù)按一定的方式組合在一在同共的協(xié)作中發(fā)揮各自的作用,它包括 使用XHTML和CSS標(biāo)準(zhǔn)化呈現(xiàn) 使用DOM實(shí)現(xiàn)動(dòng)態(tài)顯示和交互 使用XML和XSLT進(jìn)行數(shù)據(jù)交換與處理 使用XMLHttpRequest進(jìn)行異步數(shù)據(jù)讀取 最后用JavaScript綁定和處理所有數(shù)據(jù) 謝謝大家
標(biāo)簽： ajax
上傳時(shí)間： 2013-12-15
上傳用戶：c12228
A Linux port of the OpenBSD/FreeBSD Cryptographic Framework (OCF). This port aims to bring full asynchronous HW/SW crypto acceleration to the Linux kernel, OpenSwan, OpenSSL and applications using DES, 3DES, AES, MD5, SHA, PublicKey, RNGs and more.
標(biāo)簽： port Cryptographic Framework FreeBSD
上傳時(shí)間： 2016-03-29
上傳用戶：小寶愛考拉
vhdl編寫，8b—10b 編解碼器設(shè)計(jì) Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
上傳時(shí)間： 2016-05-05
上傳用戶：gundamwzc
CRC碼產(chǎn)生器與校驗(yàn)器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset
標(biāo)簽： polynomial Features Executes clock
上傳時(shí)間： 2013-12-18
上傳用戶：Ants
基于AJAX的動(dòng)態(tài)樹型結(jié)構(gòu)的設(shè)計(jì)與實(shí)現(xiàn) 簡要介紹了一種通用的，動(dòng)態(tài)樹型結(jié)構(gòu)的實(shí)現(xiàn)方案，該方案基于asynchronous JavaScript and XML，結(jié)合Struts框架設(shè)計(jì)實(shí)現(xiàn)了結(jié)構(gòu)清晰、擴(kuò)展性良好的多層架構(gòu)，數(shù)據(jù)存儲(chǔ)于數(shù)據(jù)庫，結(jié)合XML描述樹的節(jié)點(diǎn)信息，使得任何按預(yù)定的XML文檔描述的信息都可以通過動(dòng)態(tài)樹來展現(xiàn)。
標(biāo)簽： AJAX 動(dòng)態(tài) 樹
上傳時(shí)間： 2016-12-22
上傳用戶：愛死愛死
Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we needed a way of communication with a host computer, to make it available over the net.
標(biāo)簽： engineered for use Serial
上傳時(shí)間： 2017-03-11
上傳用戶：aa17807091
The use of hardware description languages (HDLs) is becoming increasingly common for designing and verifying FPGA designs. Behavior level description not only increases design productivity, but also provides unique advantages for design verification. The most dominant HDLs today are Verilog and VHDL. This application note illustrates the use of Verilog in the design and verification of a digital UART (Universal asynchronous Receiver & Transmitter).
標(biāo)簽： increasingly description designing languages
上傳時(shí)間： 2014-01-08
上傳用戶：小草123
The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external asynchronous RAM, and then send it to the computer through a serial cable
標(biāo)簽： objective project create camera
上傳時(shí)間： 2017-09-11
上傳用戶：遠(yuǎn)遠(yuǎn)ssad
基于TMS320F28035芯片為控制核心的空間矢量異步電機(jī)變頻器 我們?cè)O(shè)計(jì)的異步電機(jī)變頻調(diào)速器以TMS320F28035芯片為控制核心，通過輸出三相PWM波控制智能功率模塊IPM驅(qū)動(dòng)三相異步電機(jī)。我們使用空間矢量SVPWM算法，并對(duì)其進(jìn)行了優(yōu)化。采用檢測反電勢(shì)的方法省去了昂貴的光電編碼器，大大節(jié)省了成本。同時(shí)開創(chuàng)性的研發(fā)了自動(dòng)根據(jù)運(yùn)行環(huán)境調(diào)節(jié)的自適應(yīng)變頻算法，使我們的變頻調(diào)速器可以在電網(wǎng)條件惡劣的鄉(xiāng)村山區(qū)工作，由此該變頻器已被一家民用水泵生產(chǎn)企業(yè)預(yù)訂。關(guān)鍵字 變頻器 TMS320f28035 IPM SVPWM In our design, the asynchronous machine inverter based on the chip of TMS320F28035 drives the three-Phase asynchronous machine by sending three-phase PWM waves to the IPM, which is short for the Intelligent-Power-Module. The SVPWM (space vector pulse width modulation) strategy is applied to our control algorithm and we optimize it mainly in two aspects. Firstly the inverter detects the speed by measuring the Back EMF instead of installing an expensive photoelectric encoder for costs reduction.
標(biāo)簽： tms320f28035 芯片
上傳時(shí)間： 2022-05-08
上傳用戶：zhanglei193
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