P15V330 in video picel-rate switch applications
標(biāo)簽： applications picel-rate P15V330 switch
上傳時間： 2013-12-12
上傳用戶：wl9454
如果您不想在開發(fā)js時用alert或者想把log記錄下來您可以在頁面上引入文件后寫var log =new Log() log.info() log.error() log.warn() 來輸出您關(guān)心的東西，您將會在您的頁面上看到一個窗口，里面記錄了你輸出的東西
標(biāo)簽： log alert error info
上傳時間： 2016-11-08
上傳用戶：franktu
Error Correcting Code algorithms, for use whit E
標(biāo)簽： Correcting algorithms Error Code
上傳時間： 2014-06-20
上傳用戶：ljt101007
The ADC0803 family is a series of three CMOS 8-bit successive approximation A/D converters using a resistive ladder and capacitive array together with an auto-zero comparator. These converters are designed to operate with microprocessor-controlled buses using a minimum of external circuitry. The 3-State output data lines can be connected directly to the data bus.
標(biāo)簽： approximation converters successive family
上傳時間： 2016-11-20
上傳用戶：libenshu01
此程序為32-bit乘法器，另附有VHDL測試程序
上傳時間： 2014-01-17
上傳用戶：1583060504
基于TS201 32 bit Floating Point FIR filter
標(biāo)簽： Floating filter Point 201
上傳時間： 2013-12-17
上傳用戶：小鵬
基于TS201 32-bit floating point DFT routine
標(biāo)簽： floating routine point 201
上傳時間： 2013-12-12
上傳用戶：wendy15
1993 年兩位法國教授Berrou、Glavieux 和他們的緬甸籍博士生Thitimajshima 在ICC 會議上發(fā)表的Near Shannon limit error-correcting coding and decoding: Turbo codes”，
標(biāo)簽： error-correcting Thitimajshima Glavieux Shannon
上傳時間： 2016-12-06
上傳用戶：Avoid98
全面分析bit的概念，個人覺得很重要！！ 是自己整理的
上傳時間： 2013-11-30
上傳用戶：rishian
DDR SDRAM控制器的VHDL源代碼，含詳細(xì)設(shè)計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
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